clk: socfpga: Fix integer overflow in clock calculation

Use 64-bit integer for calculating clock rate. Also use do_div for the
64-bit division.

Signed-off-by: Graham Moore <grmoore@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index 362004e1e6fec22b7bb90ec0e7f6c3c644f1e97e..834b6e9619714a91d5b96fc0aca80a96d69cc013 100644 (file)
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -44,7 +44,8 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
                                         unsigned long parent_rate)
 {
        struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
-       unsigned long divf, divq, vco_freq, reg;
+       unsigned long divf, divq, reg;
+       unsigned long long vco_freq;
        unsigned long bypass;
 
        reg = readl(socfpgaclk->hw.reg);
@@ -54,8 +55,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
 
        divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
        divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
-       vco_freq = parent_rate * (divf + 1);
-       return vco_freq / (1 + divq);
+       vco_freq = (unsigned long long)parent_rate * (divf + 1);
+       do_div(vco_freq, (1 + divq));
+       return (unsigned long)vco_freq;
 }
 
 static struct clk_ops clk_pll_ops = {