serial: tegra: set maximum num of uart ports to 8

Set maximum number of UART ports to 8 as older chips have 5 ports and
Tergra186 and later chips will have 8 ports. Add this info to chip
data. Read device tree compatible of this driver and register uart
driver with max ports of matching chip data.

Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Link: https://lore.kernel.org/r/1567572187-29820-8-git-send-email-kyarlagadda@nvidia.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
index 69af621ff7c0134a918cb713ac3206ff0889a487..8422516a2afd9fe917fb6fcb301737006a912819 100644 (file)
--- a/drivers/tty/serial/serial-tegra.c
+++ b/drivers/tty/serial/serial-tegra.c
@@ -62,7 +62,7 @@
 #define TEGRA_UART_TX_TRIG_4B                  0x20
 #define TEGRA_UART_TX_TRIG_1B                  0x30
 
-#define TEGRA_UART_MAXIMUM                     5
+#define TEGRA_UART_MAXIMUM                     8
 
 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
 #define TEGRA_UART_DEFAULT_BAUD                        115200
@@ -87,6 +87,7 @@ struct tegra_uart_chip_data {
        bool    allow_txfifo_reset_fifo_mode;
        bool    support_clk_src_div;
        bool    fifo_mode_enable_status;
+       int     uart_max_port;
 };
 
 struct tegra_uart_port {
@@ -1322,6 +1323,7 @@ static struct tegra_uart_chip_data tegra20_uart_chip_data = {
        .allow_txfifo_reset_fifo_mode   = true,
        .support_clk_src_div            = false,
        .fifo_mode_enable_status        = false,
+       .uart_max_port                  = 5,
 };
 
 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
@@ -1329,6 +1331,7 @@ static struct tegra_uart_chip_data tegra30_uart_chip_data = {
        .allow_txfifo_reset_fifo_mode   = false,
        .support_clk_src_div            = true,
        .fifo_mode_enable_status        = false,
+       .uart_max_port                  = 5,
 };
 
 static struct tegra_uart_chip_data tegra186_uart_chip_data = {
@@ -1336,6 +1339,7 @@ static struct tegra_uart_chip_data tegra186_uart_chip_data = {
        .allow_txfifo_reset_fifo_mode   = false,
        .support_clk_src_div            = true,
        .fifo_mode_enable_status        = true,
+       .uart_max_port                  = 8,
 };
 
 static const struct of_device_id tegra_uart_of_match[] = {
@@ -1468,11 +1472,22 @@ static struct platform_driver tegra_uart_platform_driver = {
 static int __init tegra_uart_init(void)
 {
        int ret;
+       struct device_node *node;
+       const struct of_device_id *match = NULL;
+       const struct tegra_uart_chip_data *cdata = NULL;
+
+       node = of_find_matching_node(NULL, tegra_uart_of_match);
+       if (node)
+               match = of_match_node(tegra_uart_of_match, node);
+       if (match)
+               cdata = match->data;
+       if (cdata)
+               tegra_uart_driver.nr = cdata->uart_max_port;
 
        ret = uart_register_driver(&tegra_uart_driver);
        if (ret < 0) {
                pr_err("Could not register %s driver\n",
-                       tegra_uart_driver.driver_name);
+                      tegra_uart_driver.driver_name);
                return ret;
        }