LoongArch: KVM: Add address alignment check in pch_pic register access

With pch_pic device, its register is based on MMIO address space,
different access size 1/2/4/8 is supported. And base address should
be naturally aligned with its access size, here add alignment check
in its register access emulation function.

Cc: stable@vger.kernel.org
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

diff --git a/arch/loongarch/kvm/intc/pch_pic.c b/arch/loongarch/kvm/intc/pch_pic.c
index 6f00ffe05c544ecf1302c4f21a9c778f8e0da6fe..119290bcea79abf8ccd2594b583ff3d7be4789fa 100644 (file)
--- a/arch/loongarch/kvm/intc/pch_pic.c
+++ b/arch/loongarch/kvm/intc/pch_pic.c
@@ -195,6 +195,11 @@ static int kvm_pch_pic_read(struct kvm_vcpu *vcpu,
                return -EINVAL;
        }
 
+       if (addr & (len - 1)) {
+               kvm_err("%s: pch pic not aligned addr %llx len %d\n", __func__, addr, len);
+               return -EINVAL;
+       }
+
        /* statistics of pch pic reading */
        vcpu->stat.pch_pic_read_exits++;
        ret = loongarch_pch_pic_read(s, addr, len, val);
@@ -302,6 +307,11 @@ static int kvm_pch_pic_write(struct kvm_vcpu *vcpu,
                return -EINVAL;
        }
 
+       if (addr & (len - 1)) {
+               kvm_err("%s: pch pic not aligned addr %llx len %d\n", __func__, addr, len);
+               return -EINVAL;
+       }
+
        /* statistics of pch pic writing */
        vcpu->stat.pch_pic_write_exits++;
        ret = loongarch_pch_pic_write(s, addr, len, val);