ARM: dts: stm32: add FMC2 NAND controller pins muxing on stm32mp157c-ev1

This patch adds FMC2 NAND controller pins muxing used on stm32mp157c-ev1.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>

diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index df64701335741c5ed62721a24cd380c8b48f4219..c4f2b23f307f8e0a5d8ff84cc3ba0acaefa9d868 100644 (file)
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -276,6 +276,50 @@
                                };
                        };
 
+                       fmc_pins_a: fmc-0 {
+                               pins1 {
+                                       pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
+                                                <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
+                                                <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
+                                                <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
+                                                <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
+                                                <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
+                                                <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
+                                                <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
+                                                <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
+                                                <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
+                                                <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
+                                                <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
+                                                <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
+                                       bias-disable;
+                                       drive-push-pull;
+                                       slew-rate = <1>;
+                               };
+                               pins2 {
+                                       pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
+                                       bias-pull-up;
+                               };
+                       };
+
+                       fmc_sleep_pins_a: fmc-sleep-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
+                                                <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
+                                                <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
+                                                <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
+                                                <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
+                                                <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
+                                                <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
+                                                <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
+                                                <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
+                                                <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
+                                                <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
+                                                <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
+                                                <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
+                                                <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
+                               };
+                       };
+
                        i2c1_pins_a: i2c1-0 {
                                pins {
                                        pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */