arm64: dts: mediatek: mt8195: Correct clock order for dp_intf*
authorChen-Yu Tsai <wenst@chromium.org>
Fri, 2 Aug 2024 07:09:50 +0000 (15:09 +0800)
committerMatthias Brugger <matthias.bgg@gmail.com>
Mon, 9 Sep 2024 14:41:35 +0000 (16:41 +0200)
The clocks for dp_intf* device nodes are given in the wrong order,
causing the binding validation to fail.

Fixes: 6c2503b5856a ("arm64: dts: mt8195: Add dp-intf nodes")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: NĂ­colas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20240802070951.1086616-1-wenst@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
arch/arm64/boot/dts/mediatek/mt8195.dtsi

index 989e8ac545ac109a063ccaa5e8f470f00d086125..e89ba384c4aafcc444dacd02887f7a4f434d0d1b 100644 (file)
                        compatible = "mediatek,mt8195-dp-intf";
                        reg = <0 0x1c015000 0 0x1000>;
                        interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
-                       clocks = <&vdosys0  CLK_VDO0_DP_INTF0>,
-                                <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+                       clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+                                <&vdosys0  CLK_VDO0_DP_INTF0>,
                                 <&apmixedsys CLK_APMIXED_TVDPLL1>;
-                       clock-names = "engine", "pixel", "pll";
+                       clock-names = "pixel", "engine", "pll";
                        status = "disabled";
                };
 
                        reg = <0 0x1c113000 0 0x1000>;
                        interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
                        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
-                       clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
-                                <&vdosys1 CLK_VDO1_DPINTF>,
+                       clocks = <&vdosys1 CLK_VDO1_DPINTF>,
+                                <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
                                 <&apmixedsys CLK_APMIXED_TVDPLL2>;
-                       clock-names = "engine", "pixel", "pll";
+                       clock-names = "pixel", "engine", "pll";
                        status = "disabled";
                };