riscv, bpf: Optimize sign-extention mov insns with Zbb support

Add 8-bit and 16-bit sign-extention wraper with Zbb support to optimize
sign-extension mov instructions.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Acked-by: Björn Töpel <bjorn@kernel.org>
Link: https://lore.kernel.org/bpf/20240115131235.2914289-6-pulehui@huaweicloud.com

diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
index 51f6d214086fc808b0ada22653500e13d3cc87a5..b00c5c0591d2046c9bc0c34cc76d0d5f82914aed 100644 (file)
--- a/arch/riscv/net/bpf_jit.h
+++ b/arch/riscv/net/bpf_jit.h
@@ -1119,6 +1119,28 @@ static inline void emit_subw(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
                emit(rv_subw(rd, rs1, rs2), ctx);
 }
 
+static inline void emit_sextb(u8 rd, u8 rs, struct rv_jit_context *ctx)
+{
+       if (rvzbb_enabled()) {
+               emit(rvzbb_sextb(rd, rs), ctx);
+               return;
+       }
+
+       emit_slli(rd, rs, 56, ctx);
+       emit_srai(rd, rd, 56, ctx);
+}
+
+static inline void emit_sexth(u8 rd, u8 rs, struct rv_jit_context *ctx)
+{
+       if (rvzbb_enabled()) {
+               emit(rvzbb_sexth(rd, rs), ctx);
+               return;
+       }
+
+       emit_slli(rd, rs, 48, ctx);
+       emit_srai(rd, rd, 48, ctx);
+}
+
 static inline void emit_sextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
 {
        emit_addiw(rd, rs, 0, ctx);

diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index 0a26842535ea3e01da172e1406910fb2f216da7c..fc1a334e2f70d014b3e7b31f309351418ae75463 100644 (file)
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -1074,9 +1074,10 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
                        emit_mv(rd, rs, ctx);
                        break;
                case 8:
+                       emit_sextb(rd, rs, ctx);
+                       break;
                case 16:
-                       emit_slli(RV_REG_T1, rs, 64 - insn->off, ctx);
-                       emit_srai(rd, RV_REG_T1, 64 - insn->off, ctx);
+                       emit_sexth(rd, rs, ctx);
                        break;
                case 32:
                        emit_sextw(rd, rs, ctx);