drm/nouveau: move PFIFO ISR into nv04_fifo.c
authorBen Skeggs <bskeggs@redhat.com>
Wed, 3 Nov 2010 00:56:05 +0000 (10:56 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 3 Dec 2010 05:11:39 +0000 (15:11 +1000)
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_irq.c
drivers/gpu/drm/nouveau/nouveau_state.c
drivers/gpu/drm/nouveau/nv04_fifo.c
drivers/gpu/drm/nouveau/nv10_fifo.c
drivers/gpu/drm/nouveau/nv40_fifo.c
drivers/gpu/drm/nouveau/nv50_fifo.c

index c0fad126eaa411112994d4094ed039287f437c63..e174479ab67544b04e23de1c37abe6be653d06a4 100644 (file)
@@ -1053,6 +1053,7 @@ extern void nvc0_fb_takedown(struct drm_device *);
 
 /* nv04_fifo.c */
 extern int  nv04_fifo_init(struct drm_device *);
+extern void nv04_fifo_fini(struct drm_device *);
 extern void nv04_fifo_disable(struct drm_device *);
 extern void nv04_fifo_enable(struct drm_device *);
 extern bool nv04_fifo_reassign(struct drm_device *, bool);
@@ -1062,6 +1063,7 @@ extern int  nv04_fifo_create_context(struct nouveau_channel *);
 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
 extern int  nv04_fifo_load_context(struct nouveau_channel *);
 extern int  nv04_fifo_unload_context(struct drm_device *);
+extern void nv04_fifo_isr(struct drm_device *);
 
 /* nv10_fifo.c */
 extern int  nv10_fifo_init(struct drm_device *);
index 6c30669ac0b6e6a877789adca031381b7f8af0b6..16f42f774a9ef5590e7f6ec75b108ef1494f602b 100644 (file)
@@ -69,204 +69,6 @@ nouveau_irq_uninstall(struct drm_device *dev)
        nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
 }
 
-static bool
-nouveau_fifo_swmthd(struct drm_device *dev, u32 chid, u32 addr, u32 data)
-{
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nouveau_channel *chan = NULL;
-       struct nouveau_gpuobj *obj;
-       unsigned long flags;
-       const int subc = (addr >> 13) & 0x7;
-       const int mthd = addr & 0x1ffc;
-       bool handled = false;
-       u32 engine;
-
-       spin_lock_irqsave(&dev_priv->channels.lock, flags);
-       if (likely(chid >= 0 && chid < dev_priv->engine.fifo.channels))
-               chan = dev_priv->channels.ptr[chid];
-       if (unlikely(!chan))
-               goto out;
-
-       switch (mthd) {
-       case 0x0000: /* bind object to subchannel */
-               obj = nouveau_ramht_find(chan, data);
-               if (unlikely(!obj || obj->engine != NVOBJ_ENGINE_SW))
-                       break;
-
-               chan->sw_subchannel[subc] = obj->class;
-               engine = 0x0000000f << (subc * 4);
-
-               nv_mask(dev, NV04_PFIFO_CACHE1_ENGINE, engine, 0x00000000);
-               handled = true;
-               break;
-       default:
-               engine = nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE);
-               if (unlikely(((engine >> (subc * 4)) & 0xf) != 0))
-                       break;
-
-               if (!nouveau_gpuobj_mthd_call(chan, chan->sw_subchannel[subc],
-                                             mthd, data))
-                       handled = true;
-               break;
-       }
-
-out:
-       spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
-       return handled;
-}
-
-static void
-nouveau_fifo_irq_handler(struct drm_device *dev)
-{
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nouveau_engine *engine = &dev_priv->engine;
-       uint32_t status, reassign;
-       int cnt = 0;
-
-       reassign = nv_rd32(dev, NV03_PFIFO_CACHES) & 1;
-       while ((status = nv_rd32(dev, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
-               uint32_t chid, get;
-
-               nv_wr32(dev, NV03_PFIFO_CACHES, 0);
-
-               chid = engine->fifo.channel_id(dev);
-               get  = nv_rd32(dev, NV03_PFIFO_CACHE1_GET);
-
-               if (status & NV_PFIFO_INTR_CACHE_ERROR) {
-                       uint32_t mthd, data;
-                       int ptr;
-
-                       /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before
-                        * wrapping on my G80 chips, but CACHE1 isn't big
-                        * enough for this much data.. Tests show that it
-                        * wraps around to the start at GET=0x800.. No clue
-                        * as to why..
-                        */
-                       ptr = (get & 0x7ff) >> 2;
-
-                       if (dev_priv->card_type < NV_40) {
-                               mthd = nv_rd32(dev,
-                                       NV04_PFIFO_CACHE1_METHOD(ptr));
-                               data = nv_rd32(dev,
-                                       NV04_PFIFO_CACHE1_DATA(ptr));
-                       } else {
-                               mthd = nv_rd32(dev,
-                                       NV40_PFIFO_CACHE1_METHOD(ptr));
-                               data = nv_rd32(dev,
-                                       NV40_PFIFO_CACHE1_DATA(ptr));
-                       }
-
-                       if (!nouveau_fifo_swmthd(dev, chid, mthd, data)) {
-                               NV_INFO(dev, "PFIFO_CACHE_ERROR - Ch %d/%d "
-                                            "Mthd 0x%04x Data 0x%08x\n",
-                                       chid, (mthd >> 13) & 7, mthd & 0x1ffc,
-                                       data);
-                       }
-
-                       nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
-                       nv_wr32(dev, NV03_PFIFO_INTR_0,
-                                               NV_PFIFO_INTR_CACHE_ERROR);
-
-                       nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
-                               nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) & ~1);
-                       nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
-                       nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
-                               nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) | 1);
-                       nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
-
-                       nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH,
-                               nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
-                       nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
-
-                       status &= ~NV_PFIFO_INTR_CACHE_ERROR;
-               }
-
-               if (status & NV_PFIFO_INTR_DMA_PUSHER) {
-                       u32 dma_get = nv_rd32(dev, 0x003244);
-                       u32 dma_put = nv_rd32(dev, 0x003240);
-                       u32 push = nv_rd32(dev, 0x003220);
-                       u32 state = nv_rd32(dev, 0x003228);
-
-                       if (dev_priv->card_type == NV_50) {
-                               u32 ho_get = nv_rd32(dev, 0x003328);
-                               u32 ho_put = nv_rd32(dev, 0x003320);
-                               u32 ib_get = nv_rd32(dev, 0x003334);
-                               u32 ib_put = nv_rd32(dev, 0x003330);
-
-                               if (nouveau_ratelimit())
-                                       NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x "
-                                            "Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
-                                            "State 0x%08x Push 0x%08x\n",
-                                               chid, ho_get, dma_get, ho_put,
-                                               dma_put, ib_get, ib_put, state,
-                                               push);
-
-                               /* METHOD_COUNT, in DMA_STATE on earlier chipsets */
-                               nv_wr32(dev, 0x003364, 0x00000000);
-                               if (dma_get != dma_put || ho_get != ho_put) {
-                                       nv_wr32(dev, 0x003244, dma_put);
-                                       nv_wr32(dev, 0x003328, ho_put);
-                               } else
-                               if (ib_get != ib_put) {
-                                       nv_wr32(dev, 0x003334, ib_put);
-                               }
-                       } else {
-                               NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x "
-                                            "Put 0x%08x State 0x%08x Push 0x%08x\n",
-                                       chid, dma_get, dma_put, state, push);
-
-                               if (dma_get != dma_put)
-                                       nv_wr32(dev, 0x003244, dma_put);
-                       }
-
-                       nv_wr32(dev, 0x003228, 0x00000000);
-                       nv_wr32(dev, 0x003220, 0x00000001);
-                       nv_wr32(dev, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);
-                       status &= ~NV_PFIFO_INTR_DMA_PUSHER;
-               }
-
-               if (status & NV_PFIFO_INTR_SEMAPHORE) {
-                       uint32_t sem;
-
-                       status &= ~NV_PFIFO_INTR_SEMAPHORE;
-                       nv_wr32(dev, NV03_PFIFO_INTR_0,
-                               NV_PFIFO_INTR_SEMAPHORE);
-
-                       sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE);
-                       nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
-
-                       nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
-                       nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
-               }
-
-               if (dev_priv->card_type == NV_50) {
-                       if (status & 0x00000010) {
-                               nv50_fb_vm_trap(dev, 1, "PFIFO_BAR_FAULT");
-                               status &= ~0x00000010;
-                               nv_wr32(dev, 0x002100, 0x00000010);
-                       }
-               }
-
-               if (status) {
-                       if (nouveau_ratelimit())
-                               NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n",
-                                       status, chid);
-                       nv_wr32(dev, NV03_PFIFO_INTR_0, status);
-                       status = 0;
-               }
-
-               nv_wr32(dev, NV03_PFIFO_CACHES, reassign);
-       }
-
-       if (status) {
-               NV_INFO(dev, "PFIFO still angry after %d spins, halt\n", cnt);
-               nv_wr32(dev, 0x2140, 0);
-               nv_wr32(dev, 0x140, 0);
-       }
-
-       nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
-}
-
 static struct nouveau_bitfield nstatus_names[] =
 {
        { NV04_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
@@ -1146,11 +948,6 @@ nouveau_irq_handler(DRM_IRQ_ARGS)
 
        spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
 
-       if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
-               nouveau_fifo_irq_handler(dev);
-               status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
-       }
-
        if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
                if (dev_priv->card_type >= NV_50)
                        nv50_pgraph_irq_handler(dev);
index 84bff459491e06559b1cff149410ecbd8fd40bb6..262545b58d96f82e77611f14ff979f81015f7644 100644 (file)
@@ -75,7 +75,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                engine->graph.unload_context    = nv04_graph_unload_context;
                engine->fifo.channels           = 16;
                engine->fifo.init               = nv04_fifo_init;
-               engine->fifo.takedown           = nouveau_stub_takedown;
+               engine->fifo.takedown           = nv04_fifo_fini;
                engine->fifo.disable            = nv04_fifo_disable;
                engine->fifo.enable             = nv04_fifo_enable;
                engine->fifo.reassign           = nv04_fifo_reassign;
@@ -132,7 +132,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                engine->graph.set_tile_region   = nv10_graph_set_tile_region;
                engine->fifo.channels           = 32;
                engine->fifo.init               = nv10_fifo_init;
-               engine->fifo.takedown           = nouveau_stub_takedown;
+               engine->fifo.takedown           = nv04_fifo_fini;
                engine->fifo.disable            = nv04_fifo_disable;
                engine->fifo.enable             = nv04_fifo_enable;
                engine->fifo.reassign           = nv04_fifo_reassign;
@@ -189,7 +189,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                engine->graph.set_tile_region   = nv20_graph_set_tile_region;
                engine->fifo.channels           = 32;
                engine->fifo.init               = nv10_fifo_init;
-               engine->fifo.takedown           = nouveau_stub_takedown;
+               engine->fifo.takedown           = nv04_fifo_fini;
                engine->fifo.disable            = nv04_fifo_disable;
                engine->fifo.enable             = nv04_fifo_enable;
                engine->fifo.reassign           = nv04_fifo_reassign;
@@ -246,7 +246,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                engine->graph.set_tile_region   = nv20_graph_set_tile_region;
                engine->fifo.channels           = 32;
                engine->fifo.init               = nv10_fifo_init;
-               engine->fifo.takedown           = nouveau_stub_takedown;
+               engine->fifo.takedown           = nv04_fifo_fini;
                engine->fifo.disable            = nv04_fifo_disable;
                engine->fifo.enable             = nv04_fifo_enable;
                engine->fifo.reassign           = nv04_fifo_reassign;
@@ -306,7 +306,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                engine->graph.set_tile_region   = nv40_graph_set_tile_region;
                engine->fifo.channels           = 32;
                engine->fifo.init               = nv40_fifo_init;
-               engine->fifo.takedown           = nouveau_stub_takedown;
+               engine->fifo.takedown           = nv04_fifo_fini;
                engine->fifo.disable            = nv04_fifo_disable;
                engine->fifo.enable             = nv04_fifo_enable;
                engine->fifo.reassign           = nv04_fifo_reassign;
index 4c0d3a8fca68e5d8ff214ed79101ce1bb8163356..a32ba8ccaae6bdb4669d6abddbd65ad78b6f8042 100644 (file)
@@ -28,6 +28,7 @@
 #include "drm.h"
 #include "nouveau_drv.h"
 #include "nouveau_ramht.h"
+#include "nouveau_util.h"
 
 #define NV04_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV04_RAMFC__SIZE))
 #define NV04_RAMFC__SIZE 32
@@ -284,6 +285,7 @@ nv04_fifo_init_ramxx(struct drm_device *dev)
 static void
 nv04_fifo_init_intr(struct drm_device *dev)
 {
+       nouveau_irq_register(dev, 8, nv04_fifo_isr);
        nv_wr32(dev, 0x002100, 0xffffffff);
        nv_wr32(dev, 0x002140, 0xffffffff);
 }
@@ -315,3 +317,207 @@ nv04_fifo_init(struct drm_device *dev)
        return 0;
 }
 
+void
+nv04_fifo_fini(struct drm_device *dev)
+{
+       nv_wr32(dev, 0x2140, 0x00000000);
+       nouveau_irq_unregister(dev, 8);
+}
+
+static bool
+nouveau_fifo_swmthd(struct drm_device *dev, u32 chid, u32 addr, u32 data)
+{
+       struct drm_nouveau_private *dev_priv = dev->dev_private;
+       struct nouveau_channel *chan = NULL;
+       struct nouveau_gpuobj *obj;
+       unsigned long flags;
+       const int subc = (addr >> 13) & 0x7;
+       const int mthd = addr & 0x1ffc;
+       bool handled = false;
+       u32 engine;
+
+       spin_lock_irqsave(&dev_priv->channels.lock, flags);
+       if (likely(chid >= 0 && chid < dev_priv->engine.fifo.channels))
+               chan = dev_priv->channels.ptr[chid];
+       if (unlikely(!chan))
+               goto out;
+
+       switch (mthd) {
+       case 0x0000: /* bind object to subchannel */
+               obj = nouveau_ramht_find(chan, data);
+               if (unlikely(!obj || obj->engine != NVOBJ_ENGINE_SW))
+                       break;
+
+               chan->sw_subchannel[subc] = obj->class;
+               engine = 0x0000000f << (subc * 4);
+
+               nv_mask(dev, NV04_PFIFO_CACHE1_ENGINE, engine, 0x00000000);
+               handled = true;
+               break;
+       default:
+               engine = nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE);
+               if (unlikely(((engine >> (subc * 4)) & 0xf) != 0))
+                       break;
+
+               if (!nouveau_gpuobj_mthd_call(chan, chan->sw_subchannel[subc],
+                                             mthd, data))
+                       handled = true;
+               break;
+       }
+
+out:
+       spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
+       return handled;
+}
+
+void
+nv04_fifo_isr(struct drm_device *dev)
+{
+       struct drm_nouveau_private *dev_priv = dev->dev_private;
+       struct nouveau_engine *engine = &dev_priv->engine;
+       uint32_t status, reassign;
+       int cnt = 0;
+
+       reassign = nv_rd32(dev, NV03_PFIFO_CACHES) & 1;
+       while ((status = nv_rd32(dev, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
+               uint32_t chid, get;
+
+               nv_wr32(dev, NV03_PFIFO_CACHES, 0);
+
+               chid = engine->fifo.channel_id(dev);
+               get  = nv_rd32(dev, NV03_PFIFO_CACHE1_GET);
+
+               if (status & NV_PFIFO_INTR_CACHE_ERROR) {
+                       uint32_t mthd, data;
+                       int ptr;
+
+                       /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before
+                        * wrapping on my G80 chips, but CACHE1 isn't big
+                        * enough for this much data.. Tests show that it
+                        * wraps around to the start at GET=0x800.. No clue
+                        * as to why..
+                        */
+                       ptr = (get & 0x7ff) >> 2;
+
+                       if (dev_priv->card_type < NV_40) {
+                               mthd = nv_rd32(dev,
+                                       NV04_PFIFO_CACHE1_METHOD(ptr));
+                               data = nv_rd32(dev,
+                                       NV04_PFIFO_CACHE1_DATA(ptr));
+                       } else {
+                               mthd = nv_rd32(dev,
+                                       NV40_PFIFO_CACHE1_METHOD(ptr));
+                               data = nv_rd32(dev,
+                                       NV40_PFIFO_CACHE1_DATA(ptr));
+                       }
+
+                       if (!nouveau_fifo_swmthd(dev, chid, mthd, data)) {
+                               NV_INFO(dev, "PFIFO_CACHE_ERROR - Ch %d/%d "
+                                            "Mthd 0x%04x Data 0x%08x\n",
+                                       chid, (mthd >> 13) & 7, mthd & 0x1ffc,
+                                       data);
+                       }
+
+                       nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
+                       nv_wr32(dev, NV03_PFIFO_INTR_0,
+                                               NV_PFIFO_INTR_CACHE_ERROR);
+
+                       nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
+                               nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) & ~1);
+                       nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
+                       nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
+                               nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) | 1);
+                       nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
+
+                       nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH,
+                               nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
+                       nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
+
+                       status &= ~NV_PFIFO_INTR_CACHE_ERROR;
+               }
+
+               if (status & NV_PFIFO_INTR_DMA_PUSHER) {
+                       u32 dma_get = nv_rd32(dev, 0x003244);
+                       u32 dma_put = nv_rd32(dev, 0x003240);
+                       u32 push = nv_rd32(dev, 0x003220);
+                       u32 state = nv_rd32(dev, 0x003228);
+
+                       if (dev_priv->card_type == NV_50) {
+                               u32 ho_get = nv_rd32(dev, 0x003328);
+                               u32 ho_put = nv_rd32(dev, 0x003320);
+                               u32 ib_get = nv_rd32(dev, 0x003334);
+                               u32 ib_put = nv_rd32(dev, 0x003330);
+
+                               if (nouveau_ratelimit())
+                                       NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x "
+                                            "Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
+                                            "State 0x%08x Push 0x%08x\n",
+                                               chid, ho_get, dma_get, ho_put,
+                                               dma_put, ib_get, ib_put, state,
+                                               push);
+
+                               /* METHOD_COUNT, in DMA_STATE on earlier chipsets */
+                               nv_wr32(dev, 0x003364, 0x00000000);
+                               if (dma_get != dma_put || ho_get != ho_put) {
+                                       nv_wr32(dev, 0x003244, dma_put);
+                                       nv_wr32(dev, 0x003328, ho_put);
+                               } else
+                               if (ib_get != ib_put) {
+                                       nv_wr32(dev, 0x003334, ib_put);
+                               }
+                       } else {
+                               NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x "
+                                            "Put 0x%08x State 0x%08x Push 0x%08x\n",
+                                       chid, dma_get, dma_put, state, push);
+
+                               if (dma_get != dma_put)
+                                       nv_wr32(dev, 0x003244, dma_put);
+                       }
+
+                       nv_wr32(dev, 0x003228, 0x00000000);
+                       nv_wr32(dev, 0x003220, 0x00000001);
+                       nv_wr32(dev, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);
+                       status &= ~NV_PFIFO_INTR_DMA_PUSHER;
+               }
+
+               if (status & NV_PFIFO_INTR_SEMAPHORE) {
+                       uint32_t sem;
+
+                       status &= ~NV_PFIFO_INTR_SEMAPHORE;
+                       nv_wr32(dev, NV03_PFIFO_INTR_0,
+                               NV_PFIFO_INTR_SEMAPHORE);
+
+                       sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE);
+                       nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
+
+                       nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
+                       nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
+               }
+
+               if (dev_priv->card_type == NV_50) {
+                       if (status & 0x00000010) {
+                               nv50_fb_vm_trap(dev, 1, "PFIFO_BAR_FAULT");
+                               status &= ~0x00000010;
+                               nv_wr32(dev, 0x002100, 0x00000010);
+                       }
+               }
+
+               if (status) {
+                       if (nouveau_ratelimit())
+                               NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n",
+                                       status, chid);
+                       nv_wr32(dev, NV03_PFIFO_INTR_0, status);
+                       status = 0;
+               }
+
+               nv_wr32(dev, NV03_PFIFO_CACHES, reassign);
+       }
+
+       if (status) {
+               NV_INFO(dev, "PFIFO still angry after %d spins, halt\n", cnt);
+               nv_wr32(dev, 0x2140, 0);
+               nv_wr32(dev, 0x140, 0);
+       }
+
+       nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
+}
index 912556f2e33cd238fda2577b96172631166e44bc..acb9216e6d0a2cfdc35dd0f217d0074526bb4494 100644 (file)
@@ -208,6 +208,7 @@ nv10_fifo_init_ramxx(struct drm_device *dev)
 static void
 nv10_fifo_init_intr(struct drm_device *dev)
 {
+       nouveau_irq_register(dev, 8, nv04_fifo_isr);
        nv_wr32(dev, 0x002100, 0xffffffff);
        nv_wr32(dev, 0x002140, 0xffffffff);
 }
index 311ac9ea5d53e7a98fe1b19f4b30289586c48a3d..f6b3580c685aa8b7039d823da7af3449df994b33 100644 (file)
@@ -268,6 +268,7 @@ nv40_fifo_init_ramxx(struct drm_device *dev)
 static void
 nv40_fifo_init_intr(struct drm_device *dev)
 {
+       nouveau_irq_register(dev, 8, nv04_fifo_isr);
        nv_wr32(dev, 0x002100, 0xffffffff);
        nv_wr32(dev, 0x002140, 0xffffffff);
 }
index d3295aae0c4ed60e46383214f74a4ec12f9c3937..ed18952ae7f492f697c13120b39bfdc6919ac9f3 100644 (file)
@@ -106,6 +106,7 @@ nv50_fifo_init_intr(struct drm_device *dev)
 {
        NV_DEBUG(dev, "\n");
 
+       nouveau_irq_register(dev, 8, nv04_fifo_isr);
        nv_wr32(dev, NV03_PFIFO_INTR_0, 0xFFFFFFFF);
        nv_wr32(dev, NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
 }
@@ -207,6 +208,9 @@ nv50_fifo_takedown(struct drm_device *dev)
        if (!pfifo->playlist[0])
                return;
 
+       nv_wr32(dev, 0x2140, 0x00000000);
+       nouveau_irq_unregister(dev, 8);
+
        nouveau_gpuobj_ref(NULL, &pfifo->playlist[0]);
        nouveau_gpuobj_ref(NULL, &pfifo->playlist[1]);
 }