drm/i915: Extract i9xx_plane_regs.h

Relocate all pre-skl primary plane register definitions
into their own declutter i915_reg.h.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-10-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index ea4d8ba55ad802811b98f6336aa573415142c34b..1f05f9184cb24b2fc08ee9813a2bf1d9f1b00548 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -10,6 +10,7 @@
 
 #include "i915_reg.h"
 #include "i9xx_plane.h"
+#include "i9xx_plane_regs.h"
 #include "intel_atomic.h"
 #include "intel_atomic_plane.h"
 #include "intel_de.h"

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
new file mode 100644 (file)
index 0000000..0bf2cd4
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __I9XX_PLANE_REGS_H__
+#define __I9XX_PLANE_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _DSPAADDR_VLV                          0x7017C /* vlv/chv */
+#define _DSPACNTR                              0x70180
+#define   DISP_ENABLE                  REG_BIT(31)
+#define   DISP_PIPE_GAMMA_ENABLE       REG_BIT(30)
+#define   DISP_FORMAT_MASK             REG_GENMASK(29, 26)
+#define   DISP_FORMAT_8BPP             REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
+#define   DISP_FORMAT_BGRA555          REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
+#define   DISP_FORMAT_BGRX555          REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
+#define   DISP_FORMAT_BGRX565          REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
+#define   DISP_FORMAT_BGRX888          REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
+#define   DISP_FORMAT_BGRA888          REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
+#define   DISP_FORMAT_RGBX101010       REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
+#define   DISP_FORMAT_RGBA101010       REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
+#define   DISP_FORMAT_BGRX101010       REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
+#define   DISP_FORMAT_BGRA101010       REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
+#define   DISP_FORMAT_RGBX161616       REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
+#define   DISP_FORMAT_RGBX888          REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
+#define   DISP_FORMAT_RGBA888          REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
+#define   DISP_STEREO_ENABLE           REG_BIT(25)
+#define   DISP_PIPE_CSC_ENABLE         REG_BIT(24) /* ilk+ */
+#define   DISP_PIPE_SEL_MASK           REG_GENMASK(25, 24)
+#define   DISP_PIPE_SEL(pipe)          REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
+#define   DISP_SRC_KEY_ENABLE          REG_BIT(22)
+#define   DISP_LINE_DOUBLE             REG_BIT(20)
+#define   DISP_STEREO_POLARITY_SECOND  REG_BIT(18)
+#define   DISP_ALPHA_PREMULTIPLY       REG_BIT(16) /* CHV pipe B */
+#define   DISP_ROTATE_180              REG_BIT(15)
+#define   DISP_TRICKLE_FEED_DISABLE    REG_BIT(14) /* g4x+ */
+#define   DISP_TILED                   REG_BIT(10)
+#define   DISP_ASYNC_FLIP              REG_BIT(9) /* g4x+ */
+#define   DISP_MIRROR                  REG_BIT(8) /* CHV pipe B */
+#define _DSPAADDR                              0x70184
+#define _DSPASTRIDE                            0x70188
+#define _DSPAPOS                               0x7018C /* reserved */
+#define   DISP_POS_Y_MASK              REG_GENMASK(31, 16)
+#define   DISP_POS_Y(y)                        REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
+#define   DISP_POS_X_MASK              REG_GENMASK(15, 0)
+#define   DISP_POS_X(x)                        REG_FIELD_PREP(DISP_POS_X_MASK, (x))
+#define _DSPASIZE                              0x70190
+#define   DISP_HEIGHT_MASK             REG_GENMASK(31, 16)
+#define   DISP_HEIGHT(h)               REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
+#define   DISP_WIDTH_MASK              REG_GENMASK(15, 0)
+#define   DISP_WIDTH(w)                        REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
+#define _DSPASURF                              0x7019C /* 965+ only */
+#define   DISP_ADDR_MASK               REG_GENMASK(31, 12)
+#define _DSPATILEOFF                           0x701A4 /* 965+ only */
+#define   DISP_OFFSET_Y_MASK           REG_GENMASK(31, 16)
+#define   DISP_OFFSET_Y(y)             REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
+#define   DISP_OFFSET_X_MASK           REG_GENMASK(15, 0)
+#define   DISP_OFFSET_X(x)             REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
+#define _DSPAOFFSET                            0x701A4 /* HSW */
+#define _DSPASURFLIVE                          0x701AC
+#define _DSPAGAMC                              0x701E0
+
+#define DSPADDR_VLV(plane)     _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
+#define DSPCNTR(plane)         _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)
+#define DSPADDR(plane)         _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
+#define DSPSTRIDE(plane)       _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
+#define DSPPOS(plane)          _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
+#define DSPSIZE(plane)         _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
+#define DSPSURF(plane)         _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
+#define DSPTILEOFF(plane)      _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
+#define DSPLINOFF(plane)       DSPADDR(plane)
+#define DSPOFFSET(plane)       _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
+#define DSPSURFLIVE(plane)     _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
+#define DSPGAMC(plane, i)      _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
+
+/* CHV pipe B primary plane */
+#define _PRIMPOS_A             0x60a08
+#define   PRIM_POS_Y_MASK      REG_GENMASK(31, 16)
+#define   PRIM_POS_Y(y)                REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
+#define   PRIM_POS_X_MASK      REG_GENMASK(15, 0)
+#define   PRIM_POS_X(x)                REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
+#define _PRIMSIZE_A            0x60a0c
+#define   PRIM_HEIGHT_MASK     REG_GENMASK(31, 16)
+#define   PRIM_HEIGHT(h)       REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
+#define   PRIM_WIDTH_MASK      REG_GENMASK(15, 0)
+#define   PRIM_WIDTH(w)                REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
+#define _PRIMCNSTALPHA_A       0x60a10
+#define   PRIM_CONST_ALPHA_ENABLE      REG_BIT(31)
+#define   PRIM_CONST_ALPHA_MASK                REG_GENMASK(7, 0)
+#define   PRIM_CONST_ALPHA(alpha)      REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
+
+#define PRIMPOS(plane)         _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
+#define PRIMSIZE(plane)                _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)
+#define PRIMCNSTALPHA(plane)   _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
+
+#endif /* __I9XX_PLANE_REGS_H__ */

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 27224ecdc94cd6eef72fd4643020fb35b5c7a6cb..a2a827070c3369b3a44c0caf7698964b07c09bfa 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -40,6 +40,7 @@
 
 #include "i915_config.h"
 #include "i915_reg.h"
+#include "i9xx_plane_regs.h"
 #include "intel_atomic_plane.h"
 #include "intel_cdclk.h"
 #include "intel_display_rps.h"

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index d23163dc64d4ac670cd2e265d8483fc19f774ffb..82b155708422c698b282111a18327d1efb4bd893 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -22,7 +22,7 @@
  *
  */
 
-#include "i915_reg.h"
+#include "i9xx_plane_regs.h"
 #include "intel_color.h"
 #include "intel_color_regs.h"
 #include "intel_de.h"

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ee2df655b0ab930d474bb97e40302e1faefc24db..1e8e2fd52cf68930f13fb60fb6a9b94f53d5be95 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -54,6 +54,7 @@
 #include "i915_reg.h"
 #include "i915_utils.h"
 #include "i9xx_plane.h"
+#include "i9xx_plane_regs.h"
 #include "i9xx_wm.h"
 #include "intel_atomic.h"
 #include "intel_atomic_plane.h"

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 50dd8eb9012ed914d0653a5e2de03d16f1253cd5..680d7fc3950382a4894f73adc30460db9a02cea8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -48,6 +48,7 @@
 #include "i915_utils.h"
 #include "i915_vgpu.h"
 #include "i915_vma.h"
+#include "i9xx_plane_regs.h"
 #include "intel_cdclk.h"
 #include "intel_de.h"
 #include "intel_display_device.h"

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 4be8cb65fb7e7452755b96c106e97312690da94b..2c315caf2414ea45689fabe23f324361e8b2dddb 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -49,6 +49,7 @@
 #include "i915_pvinfo.h"
 #include "trace.h"
 
+#include "display/i9xx_plane_regs.h"
 #include "display/intel_display.h"
 #include "display/intel_sprite_regs.h"
 #include "gem/i915_gem_context.h"

diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 73ea8be0f80b84eeb792b6a91b8203ee6891f776..dafa13ac826b5ee392acfa5b15695527949aff40 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -37,6 +37,7 @@
 #include "gvt.h"
 
 #include "display/bxt_dpio_phy_regs.h"
+#include "display/i9xx_plane_regs.h"
 #include "display/intel_cursor_regs.h"
 #include "display/intel_display.h"
 #include "display/intel_dpio_phy.h"

diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index e78de423a6c70cabd9e0b92c7c557fd16e3fa74a..521dee39e5fbcb8bf5c23fa6ca893aec430ae473 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -40,6 +40,7 @@
 #include "i915_pvinfo.h"
 #include "i915_reg.h"
 
+#include "display/i9xx_plane_regs.h"
 #include "display/intel_cursor_regs.h"
 #include "display/intel_sprite_regs.h"
 #include "display/skl_universal_plane_regs.h"

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 6f633035618ed50e42ed9c6965f6a26a09cf84ad..27ef6dfee6418d517403747d447e0589a8b89792 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -42,6 +42,7 @@
 #include "i915_pvinfo.h"
 #include "intel_mchbar_regs.h"
 #include "display/bxt_dpio_phy_regs.h"
+#include "display/i9xx_plane_regs.h"
 #include "display/intel_cursor_regs.h"
 #include "display/intel_display_types.h"
 #include "display/intel_dmc_regs.h"

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f5e8833cc37e155f89d09502a9471240d5b97528..29f69ad8f704761766c8fde7a5c3ce2a2ab269c1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2260,75 +2260,7 @@
 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
 
-/* Display A control */
-#define _DSPAADDR_VLV                          0x7017C /* vlv/chv */
-#define _DSPACNTR                              0x70180
-#define   DISP_ENABLE                  REG_BIT(31)
-#define   DISP_PIPE_GAMMA_ENABLE       REG_BIT(30)
-#define   DISP_FORMAT_MASK             REG_GENMASK(29, 26)
-#define   DISP_FORMAT_8BPP             REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
-#define   DISP_FORMAT_BGRA555          REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
-#define   DISP_FORMAT_BGRX555          REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
-#define   DISP_FORMAT_BGRX565          REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
-#define   DISP_FORMAT_BGRX888          REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
-#define   DISP_FORMAT_BGRA888          REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
-#define   DISP_FORMAT_RGBX101010       REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
-#define   DISP_FORMAT_RGBA101010       REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
-#define   DISP_FORMAT_BGRX101010       REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
-#define   DISP_FORMAT_BGRA101010       REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
-#define   DISP_FORMAT_RGBX161616       REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
-#define   DISP_FORMAT_RGBX888          REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
-#define   DISP_FORMAT_RGBA888          REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
-#define   DISP_STEREO_ENABLE           REG_BIT(25)
-#define   DISP_PIPE_CSC_ENABLE         REG_BIT(24) /* ilk+ */
-#define   DISP_PIPE_SEL_MASK           REG_GENMASK(25, 24)
-#define   DISP_PIPE_SEL(pipe)          REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
-#define   DISP_SRC_KEY_ENABLE          REG_BIT(22)
-#define   DISP_LINE_DOUBLE             REG_BIT(20)
-#define   DISP_STEREO_POLARITY_SECOND  REG_BIT(18)
-#define   DISP_ALPHA_PREMULTIPLY       REG_BIT(16) /* CHV pipe B */
-#define   DISP_ROTATE_180              REG_BIT(15)
-#define   DISP_TRICKLE_FEED_DISABLE    REG_BIT(14) /* g4x+ */
-#define   DISP_TILED                   REG_BIT(10)
-#define   DISP_ASYNC_FLIP              REG_BIT(9) /* g4x+ */
-#define   DISP_MIRROR                  REG_BIT(8) /* CHV pipe B */
-#define _DSPAADDR                              0x70184
-#define _DSPASTRIDE                            0x70188
-#define _DSPAPOS                               0x7018C /* reserved */
-#define   DISP_POS_Y_MASK              REG_GENMASK(31, 16)
-#define   DISP_POS_Y(y)                        REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
-#define   DISP_POS_X_MASK              REG_GENMASK(15, 0)
-#define   DISP_POS_X(x)                        REG_FIELD_PREP(DISP_POS_X_MASK, (x))
-#define _DSPASIZE                              0x70190
-#define   DISP_HEIGHT_MASK             REG_GENMASK(31, 16)
-#define   DISP_HEIGHT(h)               REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
-#define   DISP_WIDTH_MASK              REG_GENMASK(15, 0)
-#define   DISP_WIDTH(w)                        REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
-#define _DSPASURF                              0x7019C /* 965+ only */
-#define   DISP_ADDR_MASK               REG_GENMASK(31, 12)
-#define _DSPATILEOFF                           0x701A4 /* 965+ only */
-#define   DISP_OFFSET_Y_MASK           REG_GENMASK(31, 16)
-#define   DISP_OFFSET_Y(y)             REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
-#define   DISP_OFFSET_X_MASK           REG_GENMASK(15, 0)
-#define   DISP_OFFSET_X(x)             REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
-#define _DSPAOFFSET                            0x701A4 /* HSW */
-#define _DSPASURFLIVE                          0x701AC
-#define _DSPAGAMC                              0x701E0
-
-#define DSPADDR_VLV(plane)     _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
-#define DSPCNTR(plane)         _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)
-#define DSPADDR(plane)         _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
-#define DSPSTRIDE(plane)       _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
-#define DSPPOS(plane)          _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
-#define DSPSIZE(plane)         _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
-#define DSPSURF(plane)         _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
-#define DSPTILEOFF(plane)      _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
-#define DSPLINOFF(plane)       DSPADDR(plane)
-#define DSPOFFSET(plane)       _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
-#define DSPSURFLIVE(plane)     _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
-#define DSPGAMC(plane, i)      _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
-
-/* CHV pipe B blender and primary plane */
+/* CHV pipe B blender */
 #define _CHV_BLEND_A           0x60a00
 #define   CHV_BLEND_MASK       REG_GENMASK(31, 30)
 #define   CHV_BLEND_LEGACY     REG_FIELD_PREP(CHV_BLEND_MASK, 0)
@@ -2338,26 +2270,9 @@
 #define   CHV_CANVAS_RED_MASK  REG_GENMASK(29, 20)
 #define   CHV_CANVAS_GREEN_MASK        REG_GENMASK(19, 10)
 #define   CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
-#define _PRIMPOS_A             0x60a08
-#define   PRIM_POS_Y_MASK      REG_GENMASK(31, 16)
-#define   PRIM_POS_Y(y)                REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
-#define   PRIM_POS_X_MASK      REG_GENMASK(15, 0)
-#define   PRIM_POS_X(x)                REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
-#define _PRIMSIZE_A            0x60a0c
-#define   PRIM_HEIGHT_MASK     REG_GENMASK(31, 16)
-#define   PRIM_HEIGHT(h)       REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
-#define   PRIM_WIDTH_MASK      REG_GENMASK(15, 0)
-#define   PRIM_WIDTH(w)                REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
-#define _PRIMCNSTALPHA_A       0x60a10
-#define   PRIM_CONST_ALPHA_ENABLE      REG_BIT(31)
-#define   PRIM_CONST_ALPHA_MASK                REG_GENMASK(7, 0)
-#define   PRIM_CONST_ALPHA(alpha)      REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
 
 #define CHV_BLEND(pipe)                _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
 #define CHV_CANVAS(pipe)       _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
-#define PRIMPOS(plane)         _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
-#define PRIMSIZE(plane)                _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)
-#define PRIMCNSTALPHA(plane)   _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
 
 /* Display/Sprite base address macros */
 #define DISP_BASEADDR_MASK     (0xfffff000)

diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 1dc5281b2adec840c9bd10d673e9b0745f26e85a..5c5685ebd49e68c6dd1385d3bb450542c2b1815f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -25,6 +25,7 @@
  *
  */
 
+#include "display/i9xx_plane_regs.h"
 #include "display/intel_de.h"
 #include "display/intel_display.h"
 #include "display/intel_display_trace.h"

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index b485976976dba472319171f5e9da13a8c10a3793..2375292292b61759c17b39c7bc0da7dfa25a7b3d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -4,6 +4,7 @@
  */
 
 #include "display/bxt_dpio_phy_regs.h"
+#include "display/i9xx_plane_regs.h"
 #include "display/intel_audio_regs.h"
 #include "display/intel_backlight_regs.h"
 #include "display/intel_color_regs.h"