arm64: dts: mediatek: mt8188: Add GPU speed bin NVMEM cells

On the MT8188, the chip is binned for different GPU voltages at the
highest OPPs. The binning value is stored in the efuse.

Add the NVMEM cell, and tie it to the GPU.

Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org>
Link: https://lore.kernel.org/r/20241213-speedbin-v1-1-a0053ead9477@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index faccc7f16259a41d52613711777fca9cb4c6da16..981853cd01920bb9bd9219a722a1e78d9b0839f2 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -2125,6 +2125,11 @@
                                reg = <0x1ac 0x40>;
                        };
 
+                       gpu_speedbin: gpu-speedbin@581 {
+                               reg = <0x581 0x1>;
+                               bits = <0 3>;
+                       };
+
                        socinfo-data1@7a0 {
                                reg = <0x7a0 0x4>;
                        };
@@ -2143,6 +2148,8 @@
                                     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
                                     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
                        interrupt-names = "job", "mmu", "gpu";
+                       nvmem-cells = <&gpu_speedbin>;
+                       nvmem-cell-names = "speed-bin";
                        operating-points-v2 = <&gpu_opp_table>;
                        power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
                                        <&spm MT8188_POWER_DOMAIN_MFG3>,