drm/amdgpu/display: drop DRM_AMD_DC_FBC kconfig option
authorAlex Deucher <alexander.deucher@amd.com>
Thu, 31 May 2018 14:09:59 +0000 (09:09 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 15 Jun 2018 17:20:29 +0000 (12:20 -0500)
Just enable it always.  This was leftover from feature
bring up.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/Kconfig
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
drivers/gpu/drm/amd/display/dc/dc.h
drivers/gpu/drm/amd/display/dc/dc_types.h
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

index d5d4586e617653b982d54ade172302c5294b9714..9d56889279b314b627a49d3862f5eabdc0b4d878 100644 (file)
@@ -9,16 +9,6 @@ config DRM_AMD_DC
          support for AMDGPU. This adds required support for Vega and
          Raven ASICs.
 
-config DRM_AMD_DC_FBC
-       bool "AMD FBC - Enable Frame Buffer Compression"
-       depends on DRM_AMD_DC
-       help
-         Choose this option if you want to use frame buffer compression
-         support.
-         This is a power optimisation feature, check its availability
-         on your hardware before enabling this option.
-
-
 config DRM_AMD_DC_DCN1_0
        bool "DCN 1.0 Raven family"
        depends on DRM_AMD_DC && X86
index d7d1245c105069059a780ce8edca83f84d41f9fd..adeb795d80f65beb4ec68245aff7f7f12e7deca4 100644 (file)
@@ -347,7 +347,6 @@ static void hotplug_notify_work_func(struct work_struct *work)
        drm_kms_helper_hotplug_event(dev);
 }
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
 /* Allocate memory for FBC compressed data  */
 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 {
@@ -388,7 +387,6 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector)
        }
 
 }
-#endif
 
 
 /* Init display KMS
@@ -3429,9 +3427,8 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
        amdgpu_dm_connector_ddc_get_modes(connector, edid);
        amdgpu_dm_connector_add_common_modes(encoder, connector);
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        amdgpu_dm_fbc_init(connector);
-#endif
+
        return amdgpu_dm_connector->num_modes;
 }
 
index d5aa89ad5571d73dbf568ce3a1067f8c485b9088..a29dc35954c9a9ec09e5585b132a3098e87f4b3e 100644 (file)
@@ -72,13 +72,11 @@ struct irq_list_head {
        struct work_struct work;
 };
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
 struct dm_comressor_info {
        void *cpu_addr;
        struct amdgpu_bo *bo_ptr;
        uint64_t gpu_addr;
 };
-#endif
 
 
 struct amdgpu_display_manager {
@@ -129,9 +127,8 @@ struct amdgpu_display_manager {
         * Caches device atomic state for suspend/resume
         */
        struct drm_atomic_state *cached_state;
-#if defined(CONFIG_DRM_AMD_DC_FBC)
+
        struct dm_comressor_info compressor;
-#endif
 };
 
 struct amdgpu_dm_connector {
index be0dee18e09f640aa9c019fec0f77cd016252185..f09fa4722fc987675b24943cf504815a0e04adc7 100644 (file)
@@ -289,9 +289,7 @@ struct dc {
        bool apply_edp_fast_boot_optimization;
 
        /* FBC compressor */
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        struct compressor *fbc_compressor;
-#endif
 };
 
 enum frame_buffer_mode {
index 7d603c53e45e7b948289b2532b00cfd48ec95e82..e026ce5ac78fd4b2dd4fe31a845675b3f949bc08 100644 (file)
@@ -92,9 +92,7 @@ struct dc_context {
        bool created_bios;
        struct gpio_service *gpio_service;
        struct i2caux *i2caux;
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        uint64_t fbc_gpu_addr;
-#endif
 };
 
 
index 111c4921987fe250b0cab9059f28bc93e6f5408e..df027013e50c4dc8452706bf219bb0298678ecbf 100644 (file)
@@ -551,9 +551,7 @@ void dce110_compressor_construct(struct dce110_compressor *compressor,
        compressor->base.lpt_channels_num = 0;
        compressor->base.attached_inst = 0;
        compressor->base.is_enabled = false;
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        compressor->base.funcs = &dce110_compressor_funcs;
 
-#endif
 }
 
index cae0054c102a1a76b199614fd64f99c75c3a9af3..1dd2ae46d505c79d7d965e4b4a03f078e785446b 100644 (file)
@@ -34,9 +34,7 @@
 #include "dce/dce_hwseq.h"
 #include "gpio_service_interface.h"
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
 #include "dce110_compressor.h"
-#endif
 
 #include "bios/bios_parser_helper.h"
 #include "timing_generator.h"
@@ -1497,10 +1495,8 @@ static void power_down_all_hw_blocks(struct dc *dc)
 
        power_down_clock_sources(dc);
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        if (dc->fbc_compressor)
                dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
-#endif
 }
 
 static void disable_vga_and_power_gate_all_controllers(
@@ -1742,9 +1738,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
        if (events->force_trigger)
                value |= 0x1;
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        value |= 0x84;
-#endif
 
        for (i = 0; i < num_pipes; i++)
                pipe_ctx[i]->stream_res.tg->funcs->
@@ -1872,8 +1866,6 @@ static void apply_min_clocks(
        }
 }
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
-
 /*
  *  Check if FBC can be enabled
  */
@@ -1952,7 +1944,6 @@ static void enable_fbc(struct dc *dc,
                compr->funcs->enable_fbc(compr, &params);
        }
 }
-#endif
 
 static void dce110_reset_hw_ctx_wrap(
                struct dc *dc,
@@ -2129,10 +2120,9 @@ enum dc_status dce110_apply_ctx_to_hw(
 
        set_safe_displaymarks(&context->res_ctx, dc->res_pool);
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        if (dc->fbc_compressor)
                dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
-#endif
+
        /*TODO: when pplib works*/
        apply_min_clocks(dc, context, &clocks_state, true);
 
@@ -2210,12 +2200,9 @@ enum dc_status dce110_apply_ctx_to_hw(
 
        dcb->funcs->set_scratch_critical_state(dcb, false);
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        if (dc->fbc_compressor)
                enable_fbc(dc, context);
 
-#endif
-
        return DC_OK;
 }
 
@@ -2530,10 +2517,9 @@ static void init_hw(struct dc *dc)
                abm->funcs->init_backlight(abm);
                abm->funcs->abm_init(abm);
        }
-#if defined(CONFIG_DRM_AMD_DC_FBC)
+
        if (dc->fbc_compressor)
                dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
-#endif
 
 }
 
@@ -2719,9 +2705,7 @@ static void dce110_program_front_end_for_pipe(
        struct dc_plane_state *plane_state = pipe_ctx->plane_state;
        struct xfm_grph_csc_adjustment adjust;
        struct out_csc_color_matrix tbl_entry;
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
-#endif
        unsigned int i;
        DC_LOGGER_INIT();
        memset(&tbl_entry, 0, sizeof(tbl_entry));
@@ -2762,7 +2746,6 @@ static void dce110_program_front_end_for_pipe(
 
        program_scaler(dc, pipe_ctx);
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        /* fbc not applicable on Underlay pipe */
        if (dc->fbc_compressor && old_pipe->stream &&
            pipe_ctx->pipe_idx != underlay_idx) {
@@ -2771,7 +2754,6 @@ static void dce110_program_front_end_for_pipe(
                else
                        enable_fbc(dc, dc->current_state);
        }
-#endif
 
        mi->funcs->mem_input_program_surface_config(
                        mi,
index ee33786bdef635279278455c2f26a5b5f19db79d..20c0290895515b775bb7a5e4f15548e4d4a3eae9 100644 (file)
@@ -54,9 +54,8 @@
 
 #define DC_LOGGER \
                dc->ctx->logger
-#if defined(CONFIG_DRM_AMD_DC_FBC)
+
 #include "dce110/dce110_compressor.h"
-#endif
 
 #include "reg_helper.h"
 
@@ -1267,12 +1266,8 @@ static bool construct(
                }
        }
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        dc->fbc_compressor = dce110_compressor_create(ctx);
 
-
-
-#endif
        if (!underlay_create(ctx, &pool->base))
                goto res_create_fail;