drm/i915/cdclk: prefer intel_de_write() over I915_WRITE()

Let's try to not add new ones while we're phasing out I915_READ() and
I915_WRITE().

Fixes: 27a6bc802bd9 ("drm/i915/dg1: Initialize RAWCLK properly")
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201130111601.2817-3-jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c449d28d0560a6f3c88f941aa82744e126ea25a2..088d5908176c403b0e10406bdd53977ecd7fdff2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2710,8 +2710,8 @@ static int dg1_rawclk(struct drm_i915_private *dev_priv)
         * DG1 always uses a 38.4 MHz rawclk.  The bspec tells us
         * "Program Numerator=2, Denominator=4, Divider=37 decimal."
         */
-       I915_WRITE(PCH_RAWCLK_FREQ,
-                  CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
+       intel_de_write(dev_priv, PCH_RAWCLK_FREQ,
+                      CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
 
        return 38400;
 }