ADL-N is pretty much the same as ADL-P (i.e., Xe_LP graphics + Xe_M
media + Xe_LPD display). However unlike ADL-P, there's no GuC hwconfig
support so the "tgl" GuC firmware should be loaded (i.e., the same
situation as ADL-S).
Acked-by: Nirmoy Das <nirmoy.das@intel.com>
Reviewed-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Link: https://lore.kernel.org/r/20230419213703.3993439-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
case XE_ROCKETLAKE:
case XE_ALDERLAKE_S:
case XE_ALDERLAKE_P:
+ case XE_ALDERLAKE_N:
info->size = ARRAY_SIZE(gen12_mocs_desc);
info->table = gen12_mocs_desc;
info->n_entries = GEN9_NUM_MOCS_ENTRIES;
},
};
+static const struct xe_device_desc adl_n_desc = {
+ .graphics = &graphics_xelp,
+ .media = &media_xem,
+ PLATFORM(XE_ALDERLAKE_N),
+ .has_llc = 1,
+ .require_force_probe = true,
+};
+
#define DGFX_FEATURES \
.is_dgfx = 1
XE_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc),
XE_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
+ XE_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
XE_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
XE_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
XE_ROCKETLAKE,
XE_ALDERLAKE_S,
XE_ALDERLAKE_P,
+ XE_ALDERLAKE_N,
XE_DG1,
XE_DG2,
XE_PVC,
[0x4] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_E0 },
};
+static const struct xe_step_info adln_revids[] = {
+ [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_D0 },
+};
+
static const struct xe_step_info dg2_g10_revid_step_tbl[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A0 },
[0x1] = { COMMON_GT_MEDIA_STEP(A1), .display = STEP_A0 },
} else if (xe->info.subplatform == XE_SUBPLATFORM_DG2_G12) {
revids = dg2_g12_revid_step_tbl;
size = ARRAY_SIZE(dg2_g12_revid_step_tbl);
+ } else if (xe->info.platform == XE_ALDERLAKE_N) {
+ revids = adln_revids;
+ size = ARRAY_SIZE(adln_revids);
} else if (xe->info.subplatform == XE_SUBPLATFORM_ADLP_RPLU) {
revids = adlp_rpl_revids;
size = ARRAY_SIZE(adlp_rpl_revids);
fw_def(PVC, mmp_ver( xe, guc, pvc, 70, 6, 4)) \
fw_def(DG2, major_ver(i915, guc, dg2, 70, 5)) \
fw_def(DG1, major_ver(i915, guc, dg1, 70, 5)) \
+ fw_def(ALDERLAKE_N, major_ver(i915, guc, tgl, 70, 5)) \
fw_def(ALDERLAKE_P, major_ver(i915, guc, adlp, 70, 5)) \
fw_def(ALDERLAKE_S, major_ver(i915, guc, tgl, 70, 5)) \
fw_def(ROCKETLAKE, major_ver(i915, guc, tgl, 70, 5)) \