arm64: dts: st: OP-TEE async notif on PPI 15 for stm32mp25

Define GIC PPI 15 (aka GIC interrupt line 31) for OP-TEE asynchronous
notification.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index dcd0656d67a807d07062d992204c9a1b7d5aa1ce..22a5379ea1c9d33b79afc6d62e4697acfee05c4b 100644 (file)
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -51,9 +51,11 @@
        };
 
        firmware {
-               optee {
+               optee: optee {
                        compatible = "linaro,optee-tz";
                        method = "smc";
+                       interrupt-parent = <&intc>;
+                       interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
                };
 
                scmi {

diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi
index 029f8898196167d2300e06c4a4750d1e5e0b0c65..69001f924d17c677b130624efb1734921aff4a6c 100644 (file)
--- a/arch/arm64/boot/dts/st/stm32mp253.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi
@@ -28,3 +28,7 @@
                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
        };
 };
+
+&optee {
+       interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+};