Merge remote-tracking branches 'spi/topic/orion', 'spi/topic/pxa2xx', 'spi/topic...

diff --combined drivers/spi/Kconfig
index 5ade0b86a0be925c863c019c896ca8809d66e224,99829985c1a194ebe6edc0e73912077bade693d3,99829985c1a194ebe6edc0e73912077bade693d3,99829985c1a194ebe6edc0e73912077bade693d3,99829985c1a194ebe6edc0e73912077bade693d3,d4020608bab6a279fa56575ceba4d8a7365b5936..1f2e411cdf464cff44dfa6aee999b831736798b0
--- 1/drivers/spi/Kconfig
--- 2/drivers/spi/Kconfig
--- 3/drivers/spi/Kconfig
--- 4/drivers/spi/Kconfig
--- 5/drivers/spi/Kconfig
--- 6/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@@@@@@ -185,16 -185,6 -185,6 -185,6 -185,6 -185,6 +185,16 @@@@@@@ config SPI_DAVINC
        help
          SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules.
      
 +++++config SPI_DLN2
 +++++       tristate "Diolan DLN-2 USB SPI adapter"
 +++++       depends on MFD_DLN2
 +++++       help
 +++++         If you say yes to this option, support will be included for Diolan
 +++++         DLN2, a USB to SPI interface.
 +++++
 +++++         This driver can also be built as a module.  If so, the module
 +++++         will be called spi-dln2.
 +++++
      config SPI_EFM32
        tristate "EFM32 SPI controller"
        depends on OF && ARM && (ARCH_EFM32 || COMPILE_TEST)
@@@@@@@ -289,7 -279,7 -279,7 -279,7 -279,7 -279,7 +289,7 @@@@@@@ config SPI_FSL_CP
        depends on FSL_SOC
      
      config SPI_FSL_SPI
 -----  bool "Freescale SPI controller and Aeroflex Gaisler GRLIB SPI controller"
 +++++  tristate "Freescale SPI controller and Aeroflex Gaisler GRLIB SPI controller"
        depends on OF
        select SPI_FSL_LIB
        select SPI_FSL_CPM if FSL_SOC
@@@@@@@ -302,6 -292,7 -292,7 -292,7 -292,7 -292,7 +302,6 @@@@@@@
      
      config SPI_FSL_DSPI
        tristate "Freescale DSPI controller"
 -----  select SPI_BITBANG
        select REGMAP_MMIO
        depends on SOC_VF610 || COMPILE_TEST
        help
@@@@@@@ -309,7 -300,7 -300,7 -300,7 -300,7 -300,7 +309,7 @@@@@@@
          mode. VF610 platform uses the controller.
      
      config SPI_FSL_ESPI
 -----  bool "Freescale eSPI controller"
 +++++  tristate "Freescale eSPI controller"
        depends on FSL_SOC
        select SPI_FSL_LIB
        help
@@@@@@@ -469,7 -460,7 -460,7 -460,7 -460,7 -460,6 +469,6 @@@@@@@ config SPI_S3C24XX_FI
      config SPI_S3C64XX
        tristate "Samsung S3C64XX series type SPI"
        depends on (PLAT_SAMSUNG || ARCH_EXYNOS)
-----   select S3C64XX_PL080 if ARCH_S3C64XX
        help
          SPI driver for Samsung S3C64XX and newer SoCs.
      
@@@@@@@ -604,6 -595,7 -595,7 -595,7 -595,7 -594,7 +603,6 @@@@@@@ config SPI_XTENSA_XTFPG
          16 bit words in SPI mode 0, automatically asserting CS on transfer
          start and deasserting on end.
      
 -----
      config SPI_NUC900
        tristate "Nuvoton NUC900 series SPI"
        depends on ARCH_W90X900

diff --combined drivers/spi/spi-pxa2xx-pxadma.c
index e51fcf9fd39bfbec091344379b7f7fb3d255ca80,e8a26f25d5c0a1464ab259c545e2b1d2031a9741,3fecaaa5b0a58390fac737a19bdc195a2fed5780,e8a26f25d5c0a1464ab259c545e2b1d2031a9741,e8a26f25d5c0a1464ab259c545e2b1d2031a9741,e8a26f25d5c0a1464ab259c545e2b1d2031a9741..2e0796a0003f470a56508180be7c75a7a505983f
--- 1/drivers/spi/spi-pxa2xx-pxadma.c
--- 2/drivers/spi/spi-pxa2xx-pxadma.c
--- 3/drivers/spi/spi-pxa2xx-pxadma.c
--- 4/drivers/spi/spi-pxa2xx-pxadma.c
--- 5/drivers/spi/spi-pxa2xx-pxadma.c
--- 6/drivers/spi/spi-pxa2xx-pxadma.c
+++ b/drivers/spi/spi-pxa2xx-pxadma.c
@@@@@@@ -12,6 -12,10 -12,10 -12,10 -12,10 -12,10 +12,6 @@@@@@@
       * but WITHOUT ANY WARRANTY; without even the implied warranty of
       * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
       * GNU General Public License for more details.
 ----- *
 ----- * You should have received a copy of the GNU General Public License
 ----- * along with this program; if not, write to the Free Software
 ----- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
       */
      
      #include <linux/delay.h>
@@@@@@@ -21,6 -25,6 -25,7 -25,6 -25,6 -25,6 +21,7 @@@@@@@
      #include <linux/spi/spi.h>
      #include <linux/spi/pxa2xx_spi.h>
      
++ +++#include <mach/dma.h>
      #include "spi-pxa2xx.h"
      
      #define DMA_INT_MASK              (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
@@@@@@@ -114,11 -118,11 -119,11 -118,11 -118,11 -118,11 +115,11 @@@@@@@ static void pxa2xx_spi_unmap_dma_buffer
        drv_data->dma_mapped = 0;
      }
      
-- ---static int wait_ssp_rx_stall(void const __iomem *ioaddr)
++ +++static int wait_ssp_rx_stall(struct driver_data *drv_data)
      {
        unsigned long limit = loops_per_jiffy << 1;
      
-- ---  while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit)
++ +++  while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit)
                cpu_relax();
      
        return limit;
@@@@@@@ -137,17 -141,17 -142,18 -141,17 -141,17 -141,17 +138,18 @@@@@@@ static int wait_dma_channel_stop(int ch
      static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data,
                                      const char *msg)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
-- ---
        /* Stop and reset */
        DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
        DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
        write_SSSR_CS(drv_data, drv_data->clear_sr);
-- ---  write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
++ +++  pxa2xx_spi_write(drv_data, SSCR1,
++ +++                   pxa2xx_spi_read(drv_data, SSCR1)
++ +++                   & ~drv_data->dma_cr1);
        if (!pxa25x_ssp_comp(drv_data))
-- ---          write_SSTO(0, reg);
++ +++          pxa2xx_spi_write(drv_data, SSTO, 0);
        pxa2xx_spi_flush(drv_data);
-- ---  write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
++ +++  pxa2xx_spi_write(drv_data, SSCR0,
++ +++                   pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
      
        pxa2xx_spi_unmap_dma_buffers(drv_data);
      
@@@@@@@ -159,11 -163,11 -165,12 -163,11 -163,11 -163,11 +161,12 @@@@@@@
      
      static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
        struct spi_message *msg = drv_data->cur_msg;
      
        /* Clear and disable interrupts on SSP and DMA channels*/
-- ---  write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
++ +++  pxa2xx_spi_write(drv_data, SSCR1,
++ +++                   pxa2xx_spi_read(drv_data, SSCR1)
++ +++                   & ~drv_data->dma_cr1);
        write_SSSR_CS(drv_data, drv_data->clear_sr);
        DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
        DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
@@@@@@@ -224,7 -228,7 -231,7 -228,7 -228,7 -228,7 +227,7 @@@@@@@ void pxa2xx_spi_dma_handler(int channel
                && (drv_data->ssp_type == PXA25x_SSP)) {
      
                /* Wait for rx to stall */
-- ---          if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
++ +++          if (wait_ssp_rx_stall(drv_data) == 0)
                        dev_err(&drv_data->pdev->dev,
                                "dma_handler: ssp rx stall failed\n");
      
@@@@@@@ -236,9 -240,9 -243,8 -240,9 -240,9 -240,9 +239,8 @@@@@@@
      irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
      {
        u32 irq_status;
-- ---  void __iomem *reg = drv_data->ioaddr;
      
-- ---  irq_status = read_SSSR(reg) & drv_data->mask_sr;
++ +++  irq_status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
        if (irq_status & SSSR_ROR) {
                pxa2xx_spi_dma_error_stop(drv_data,
                                          "dma_transfer: fifo overrun");
@@@@@@@ -248,7 -252,7 -254,7 -252,7 -252,7 -252,7 +250,7 @@@@@@@
        /* Check for false positive timeout */
        if ((irq_status & SSSR_TINT)
                && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
-- ---          write_SSSR(SSSR_TINT, reg);
++ +++          pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
                return IRQ_HANDLED;
        }
      
@@@@@@@ -257,7 -261,7 -263,7 -261,7 -261,7 -261,7 +259,7 @@@@@@@
                /* Clear and disable timeout interrupt, do the rest in
                 * dma_transfer_complete */
                if (!pxa25x_ssp_comp(drv_data))
-- ---                  write_SSTO(0, reg);
++ +++                  pxa2xx_spi_write(drv_data, SSTO, 0);
      
                /* finish this transfer, start the next */
                pxa2xx_spi_dma_transfer_complete(drv_data);

diff --combined drivers/spi/spi-pxa2xx.c
index 24a4951be46bf5d5e35dcd54f1b25728c612716d,05c623cfb078d6503bd6d501cc1e821f07784d9e,bbf3c93f12bd358c42ec696ae0f3d35cbe9ad2c9,05c623cfb078d6503bd6d501cc1e821f07784d9e,05c623cfb078d6503bd6d501cc1e821f07784d9e,05c623cfb078d6503bd6d501cc1e821f07784d9e..6f72ad01e0410257a42bc8739f8962abfbaf3b5e
--- 1/drivers/spi/spi-pxa2xx.c
--- 2/drivers/spi/spi-pxa2xx.c
--- 3/drivers/spi/spi-pxa2xx.c
--- 4/drivers/spi/spi-pxa2xx.c
--- 5/drivers/spi/spi-pxa2xx.c
--- 6/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@@@@@@ -11,6 -11,10 -11,10 -11,10 -11,10 -11,10 +11,6 @@@@@@@
       * but WITHOUT ANY WARRANTY; without even the implied warranty of
       * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
       * GNU General Public License for more details.
 ----- *
 ----- * You should have received a copy of the GNU General Public License
 ----- * along with this program; if not, write to the Free Software
 ----- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
       */
      
      #include <linux/init.h>
@@@@@@@ -41,8 -45,8 -45,6 -45,8 -45,8 -45,8 +41,6 @@@@@@@ MODULE_DESCRIPTION("PXA2xx SSP SPI Cont
      MODULE_LICENSE("GPL");
      MODULE_ALIAS("platform:pxa2xx-spi");
      
-- ---#define MAX_BUSES 3
-- ---
      #define TIMOUT_DFLT               1000
      
      /*
@@@@@@@ -158,7 -162,7 -160,6 -162,7 -162,7 -162,7 +156,6 @@@@@@@ pxa2xx_spi_get_rx_default_thre(const st
      
      static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
        u32 mask;
      
        switch (drv_data->ssp_type) {
@@@@@@@ -170,7 -174,7 -171,7 -174,7 -174,7 -174,7 +167,7 @@@@@@@
                break;
        }
      
-- ---  return (read_SSSR(reg) & mask) == mask;
++ +++  return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
      }
      
      static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
@@@@@@@ -249,9 -253,9 -250,6 -253,9 -253,9 -253,9 +246,6 @@@@@@@ static void lpss_ssp_setup(struct drive
        unsigned offset = 0x400;
        u32 value, orig;
      
-- ---  if (!is_lpss_ssp(drv_data))
-- ---          return;
-- ---
        /*
         * Perform auto-detection of the LPSS SSP private registers. They
         * can be either at 1k or 2k offset from the base address.
@@@@@@@ -300,9 -304,9 -298,6 -304,9 -304,9 -304,9 +294,6 @@@@@@@ static void lpss_ssp_cs_control(struct 
      {
        u32 value;
      
-- ---  if (!is_lpss_ssp(drv_data))
-- ---          return;
-- ---
        value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
        if (enable)
                value &= ~SPI_CS_CONTROL_CS_HIGH;
@@@@@@@ -316,7 -320,7 -311,7 -320,7 -320,7 -320,7 +307,7 @@@@@@@ static void cs_assert(struct driver_dat
        struct chip_data *chip = drv_data->cur_chip;
      
        if (drv_data->ssp_type == CE4100_SSP) {
-- ---          write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
++ +++          pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
                return;
        }
      
@@@@@@@ -330,7 -334,7 -325,8 -334,7 -334,7 -334,7 +321,8 @@@@@@@
                return;
        }
      
-- ---  lpss_ssp_cs_control(drv_data, true);
++ +++  if (is_lpss_ssp(drv_data))
++ +++          lpss_ssp_cs_control(drv_data, true);
      }
      
      static void cs_deassert(struct driver_data *drv_data)
@@@@@@@ -350,20 -354,20 -346,18 -354,20 -354,20 -354,20 +342,18 @@@@@@@
                return;
        }
      
-- ---  lpss_ssp_cs_control(drv_data, false);
++ +++  if (is_lpss_ssp(drv_data))
++ +++          lpss_ssp_cs_control(drv_data, false);
      }
      
      int pxa2xx_spi_flush(struct driver_data *drv_data)
      {
        unsigned long limit = loops_per_jiffy << 1;
      
-- ---  void __iomem *reg = drv_data->ioaddr;
-- ---
        do {
-- ---          while (read_SSSR(reg) & SSSR_RNE) {
-- ---                  read_SSDR(reg);
-- ---          }
-- ---  } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
++ +++          while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
++ +++                  pxa2xx_spi_read(drv_data, SSDR);
++ +++  } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
        write_SSSR_CS(drv_data, SSSR_ROR);
      
        return limit;
@@@@@@@ -371,14 -375,14 -365,13 -375,14 -375,14 -375,14 +361,13 @@@@@@@
      
      static int null_writer(struct driver_data *drv_data)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
        u8 n_bytes = drv_data->n_bytes;
      
        if (pxa2xx_spi_txfifo_full(drv_data)
                || (drv_data->tx == drv_data->tx_end))
                return 0;
      
-- ---  write_SSDR(0, reg);
++ +++  pxa2xx_spi_write(drv_data, SSDR, 0);
        drv_data->tx += n_bytes;
      
        return 1;
@@@@@@@ -386,12 -390,12 -379,11 -390,12 -390,12 -390,12 +375,11 @@@@@@@
      
      static int null_reader(struct driver_data *drv_data)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
        u8 n_bytes = drv_data->n_bytes;
      
-- ---  while ((read_SSSR(reg) & SSSR_RNE)
-- ---          && (drv_data->rx < drv_data->rx_end)) {
-- ---          read_SSDR(reg);
++ +++  while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
++ +++         && (drv_data->rx < drv_data->rx_end)) {
++ +++          pxa2xx_spi_read(drv_data, SSDR);
                drv_data->rx += n_bytes;
        }
      
@@@@@@@ -400,13 -404,13 -392,11 -404,13 -404,13 -404,13 +388,11 @@@@@@@
      
      static int u8_writer(struct driver_data *drv_data)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
-- ---
        if (pxa2xx_spi_txfifo_full(drv_data)
                || (drv_data->tx == drv_data->tx_end))
                return 0;
      
-- ---  write_SSDR(*(u8 *)(drv_data->tx), reg);
++ +++  pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
        ++drv_data->tx;
      
        return 1;
@@@@@@@ -414,11 -418,11 -404,9 -418,11 -418,11 -418,11 +400,9 @@@@@@@
      
      static int u8_reader(struct driver_data *drv_data)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
-- ---
-- ---  while ((read_SSSR(reg) & SSSR_RNE)
-- ---          && (drv_data->rx < drv_data->rx_end)) {
-- ---          *(u8 *)(drv_data->rx) = read_SSDR(reg);
++ +++  while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
++ +++         && (drv_data->rx < drv_data->rx_end)) {
++ +++          *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
                ++drv_data->rx;
        }
      
@@@@@@@ -427,13 -431,13 -415,11 -431,13 -431,13 -431,13 +411,11 @@@@@@@
      
      static int u16_writer(struct driver_data *drv_data)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
-- ---
        if (pxa2xx_spi_txfifo_full(drv_data)
                || (drv_data->tx == drv_data->tx_end))
                return 0;
      
-- ---  write_SSDR(*(u16 *)(drv_data->tx), reg);
++ +++  pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
        drv_data->tx += 2;
      
        return 1;
@@@@@@@ -441,11 -445,11 -427,9 -445,11 -445,11 -445,11 +423,9 @@@@@@@
      
      static int u16_reader(struct driver_data *drv_data)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
-- ---
-- ---  while ((read_SSSR(reg) & SSSR_RNE)
-- ---          && (drv_data->rx < drv_data->rx_end)) {
-- ---          *(u16 *)(drv_data->rx) = read_SSDR(reg);
++ +++  while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
++ +++         && (drv_data->rx < drv_data->rx_end)) {
++ +++          *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
                drv_data->rx += 2;
        }
      
@@@@@@@ -454,13 -458,13 -438,11 -458,13 -458,13 -458,13 +434,11 @@@@@@@
      
      static int u32_writer(struct driver_data *drv_data)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
-- ---
        if (pxa2xx_spi_txfifo_full(drv_data)
                || (drv_data->tx == drv_data->tx_end))
                return 0;
      
-- ---  write_SSDR(*(u32 *)(drv_data->tx), reg);
++ +++  pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
        drv_data->tx += 4;
      
        return 1;
@@@@@@@ -468,11 -472,11 -450,9 -472,11 -472,11 -472,11 +446,9 @@@@@@@
      
      static int u32_reader(struct driver_data *drv_data)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
-- ---
-- ---  while ((read_SSSR(reg) & SSSR_RNE)
-- ---          && (drv_data->rx < drv_data->rx_end)) {
-- ---          *(u32 *)(drv_data->rx) = read_SSDR(reg);
++ +++  while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
++ +++         && (drv_data->rx < drv_data->rx_end)) {
++ +++          *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
                drv_data->rx += 4;
        }
      
@@@@@@@ -542,33 -546,33 -522,31 -546,33 -546,33 -546,33 +518,31 @@@@@@@ static void giveback(struct driver_dat
                        cs_deassert(drv_data);
        }
      
 -----  spi_finalize_current_message(drv_data->master);
        drv_data->cur_chip = NULL;
 +++++  spi_finalize_current_message(drv_data->master);
      }
      
      static void reset_sccr1(struct driver_data *drv_data)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
        struct chip_data *chip = drv_data->cur_chip;
        u32 sccr1_reg;
      
-- ---  sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
++ +++  sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
        sccr1_reg &= ~SSCR1_RFT;
        sccr1_reg |= chip->threshold;
-- ---  write_SSCR1(sccr1_reg, reg);
++ +++  pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
      }
      
      static void int_error_stop(struct driver_data *drv_data, const char* msg)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
-- ---
        /* Stop and reset SSP */
        write_SSSR_CS(drv_data, drv_data->clear_sr);
        reset_sccr1(drv_data);
        if (!pxa25x_ssp_comp(drv_data))
-- ---          write_SSTO(0, reg);
++ +++          pxa2xx_spi_write(drv_data, SSTO, 0);
        pxa2xx_spi_flush(drv_data);
-- ---  write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
++ +++  pxa2xx_spi_write(drv_data, SSCR0,
++ +++                   pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
      
        dev_err(&drv_data->pdev->dev, "%s\n", msg);
      
@@@@@@@ -578,13 -582,13 -556,11 -582,13 -582,13 -582,13 +552,11 @@@@@@@
      
      static void int_transfer_complete(struct driver_data *drv_data)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
-- ---
        /* Stop SSP */
        write_SSSR_CS(drv_data, drv_data->clear_sr);
        reset_sccr1(drv_data);
        if (!pxa25x_ssp_comp(drv_data))
-- ---          write_SSTO(0, reg);
++ +++          pxa2xx_spi_write(drv_data, SSTO, 0);
      
        /* Update total byte transferred return count actual bytes read */
        drv_data->cur_msg->actual_length += drv_data->len -
@@@@@@@ -603,12 -607,12 -579,10 -607,12 -607,12 -607,12 +575,10 @@@@@@@
      
      static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
      {
-- ---  void __iomem *reg = drv_data->ioaddr;
++ +++  u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
++ +++                 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
      
-- ---  u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
-- ---                  drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
-- ---
-- ---  u32 irq_status = read_SSSR(reg) & irq_mask;
++ +++  u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
      
        if (irq_status & SSSR_ROR) {
                int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
@@@@@@@ -616,7 -620,7 -590,7 -620,7 -620,7 -620,7 +586,7 @@@@@@@
        }
      
        if (irq_status & SSSR_TINT) {
-- ---          write_SSSR(SSSR_TINT, reg);
++ +++          pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
                if (drv_data->read(drv_data)) {
                        int_transfer_complete(drv_data);
                        return IRQ_HANDLED;
@@@@@@@ -640,7 -644,7 -614,7 -644,7 -644,7 -644,7 +610,7 @@@@@@@
                u32 bytes_left;
                u32 sccr1_reg;
      
-- ---          sccr1_reg = read_SSCR1(reg);
++ +++          sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
                sccr1_reg &= ~SSCR1_TIE;
      
                /*
@@@@@@@ -666,7 -670,7 -640,7 -670,7 -670,7 -670,7 +636,7 @@@@@@@
      
                        pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
                }
-- ---          write_SSCR1(sccr1_reg, reg);
++ +++          pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
        }
      
        /* We did something */
@@@@@@@ -676,7 -680,7 -650,6 -680,7 -680,7 -680,7 +646,6 @@@@@@@
      static irqreturn_t ssp_int(int irq, void *dev_id)
      {
        struct driver_data *drv_data = dev_id;
-- ---  void __iomem *reg = drv_data->ioaddr;
        u32 sccr1_reg;
        u32 mask = drv_data->mask_sr;
        u32 status;
@@@@@@@ -696,11 -700,11 -669,11 -700,11 -700,11 -700,11 +665,11 @@@@@@@
         * are all set to one. That means that the device is already
         * powered off.
         */
-- ---  status = read_SSSR(reg);
++ +++  status = pxa2xx_spi_read(drv_data, SSSR);
        if (status == ~0)
                return IRQ_NONE;
      
-- ---  sccr1_reg = read_SSCR1(reg);
++ +++  sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
      
        /* Ignore possible writes if we don't need to write */
        if (!(sccr1_reg & SSCR1_TIE))
@@@@@@@ -711,10 -715,10 -684,14 -715,10 -715,10 -715,10 +680,14 @@@@@@@
      
        if (!drv_data->cur_msg) {
      
-- ---          write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
-- ---          write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
++ +++          pxa2xx_spi_write(drv_data, SSCR0,
++ +++                           pxa2xx_spi_read(drv_data, SSCR0)
++ +++                           & ~SSCR0_SSE);
++ +++          pxa2xx_spi_write(drv_data, SSCR1,
++ +++                           pxa2xx_spi_read(drv_data, SSCR1)
++ +++                           & ~drv_data->int_cr1);
                if (!pxa25x_ssp_comp(drv_data))
-- ---                  write_SSTO(0, reg);
++ +++                  pxa2xx_spi_write(drv_data, SSTO, 0);
                write_SSSR_CS(drv_data, drv_data->clear_sr);
      
                dev_err(&drv_data->pdev->dev,
@@@@@@@ -783,7 -787,7 -760,6 -787,7 -787,7 -787,7 +756,6 @@@@@@@ static void pump_transfers(unsigned lon
        struct spi_transfer *transfer = NULL;
        struct spi_transfer *previous = NULL;
        struct chip_data *chip = NULL;
-- ---  void __iomem *reg = drv_data->ioaddr;
        u32 clk_div = 0;
        u8 bits = 0;
        u32 speed = 0;
@@@@@@@ -927,7 -931,7 -903,7 -931,7 -931,7 -931,7 +899,7 @@@@@@@
      
                /* Clear status and start DMA engine */
                cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
-- ---          write_SSSR(drv_data->clear_sr, reg);
++ +++          pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
      
                pxa2xx_spi_dma_start(drv_data);
        } else {
@@@@@@@ -940,39 -944,39 -916,43 -944,39 -944,39 -944,39 +912,43 @@@@@@@
        }
      
        if (is_lpss_ssp(drv_data)) {
-- ---          if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
-- ---                  write_SSIRF(chip->lpss_rx_threshold, reg);
-- ---          if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
-- ---                  write_SSITF(chip->lpss_tx_threshold, reg);
++ +++          if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
++ +++              != chip->lpss_rx_threshold)
++ +++                  pxa2xx_spi_write(drv_data, SSIRF,
++ +++                                   chip->lpss_rx_threshold);
++ +++          if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
++ +++              != chip->lpss_tx_threshold)
++ +++                  pxa2xx_spi_write(drv_data, SSITF,
++ +++                                   chip->lpss_tx_threshold);
        }
      
        if (is_quark_x1000_ssp(drv_data) &&
-- ---      (read_DDS_RATE(reg) != chip->dds_rate))
-- ---          write_DDS_RATE(chip->dds_rate, reg);
++ +++      (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
++ +++          pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
      
        /* see if we need to reload the config registers */
-- ---  if ((read_SSCR0(reg) != cr0) ||
-- ---      (read_SSCR1(reg) & change_mask) != (cr1 & change_mask)) {
-- ---
++ +++  if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
++ +++      || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
++ +++      != (cr1 & change_mask)) {
                /* stop the SSP, and update the other bits */
-- ---          write_SSCR0(cr0 & ~SSCR0_SSE, reg);
++ +++          pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
                if (!pxa25x_ssp_comp(drv_data))
-- ---                  write_SSTO(chip->timeout, reg);
++ +++                  pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
                /* first set CR1 without interrupt and service enables */
-- ---          write_SSCR1(cr1 & change_mask, reg);
++ +++          pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
                /* restart the SSP */
-- ---          write_SSCR0(cr0, reg);
++ +++          pxa2xx_spi_write(drv_data, SSCR0, cr0);
      
        } else {
                if (!pxa25x_ssp_comp(drv_data))
-- ---                  write_SSTO(chip->timeout, reg);
++ +++                  pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
        }
      
        cs_assert(drv_data);
      
        /* after chip select, release the data by enabling service
         * requests and interrupts, without changing any mode bits */
-- ---  write_SSCR1(cr1, reg);
++ +++  pxa2xx_spi_write(drv_data, SSCR1, cr1);
      }
      
      static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
@@@@@@@ -1001,8 -1005,8 -981,8 -1005,8 -1005,8 -1005,8 +977,8 @@@@@@@ static int pxa2xx_spi_unprepare_transfe
        struct driver_data *drv_data = spi_master_get_devdata(master);
      
        /* Disable the SSP now */
-- ---  write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE,
-- ---              drv_data->ioaddr);
++ +++  pxa2xx_spi_write(drv_data, SSCR0,
++ +++                   pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
      
        return 0;
      }
@@@@@@@ -1285,6 -1289,6 -1265,7 -1289,6 -1289,6 -1289,6 +1261,7 @@@@@@@ static int pxa2xx_spi_probe(struct plat
        struct driver_data *drv_data;
        struct ssp_device *ssp;
        int status;
++ +++  u32 tmp;
      
        platform_info = dev_get_platdata(dev);
        if (!platform_info) {
@@@@@@@ -1382,38 -1386,38 -1363,35 -1386,38 -1386,38 -1386,38 +1359,35 @@@@@@@
        drv_data->max_clk_rate = clk_get_rate(ssp->clk);
      
        /* Load default SSP configuration */
-- ---  write_SSCR0(0, drv_data->ioaddr);
++ +++  pxa2xx_spi_write(drv_data, SSCR0, 0);
        switch (drv_data->ssp_type) {
        case QUARK_X1000_SSP:
-- ---          write_SSCR1(QUARK_X1000_SSCR1_RxTresh(
-- ---                                  RX_THRESH_QUARK_X1000_DFLT) |
-- ---                      QUARK_X1000_SSCR1_TxTresh(
-- ---                                  TX_THRESH_QUARK_X1000_DFLT),
-- ---                      drv_data->ioaddr);
++ +++          tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
++ +++                | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
++ +++          pxa2xx_spi_write(drv_data, SSCR1, tmp);
      
                /* using the Motorola SPI protocol and use 8 bit frame */
-- ---          write_SSCR0(QUARK_X1000_SSCR0_Motorola
-- ---                      | QUARK_X1000_SSCR0_DataSize(8),
-- ---                      drv_data->ioaddr);
++ +++          pxa2xx_spi_write(drv_data, SSCR0,
++ +++                           QUARK_X1000_SSCR0_Motorola
++ +++                           | QUARK_X1000_SSCR0_DataSize(8));
                break;
        default:
-- ---          write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
-- ---                      SSCR1_TxTresh(TX_THRESH_DFLT),
-- ---                      drv_data->ioaddr);
-- ---          write_SSCR0(SSCR0_SCR(2)
-- ---                      | SSCR0_Motorola
-- ---                      | SSCR0_DataSize(8),
-- ---                      drv_data->ioaddr);
++ +++          tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
++ +++                SSCR1_TxTresh(TX_THRESH_DFLT);
++ +++          pxa2xx_spi_write(drv_data, SSCR1, tmp);
++ +++          tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
++ +++          pxa2xx_spi_write(drv_data, SSCR0, tmp);
                break;
        }
      
        if (!pxa25x_ssp_comp(drv_data))
-- ---          write_SSTO(0, drv_data->ioaddr);
++ +++          pxa2xx_spi_write(drv_data, SSTO, 0);
      
        if (!is_quark_x1000_ssp(drv_data))
-- ---          write_SSPSP(0, drv_data->ioaddr);
++ +++          pxa2xx_spi_write(drv_data, SSPSP, 0);
      
-- ---  lpss_ssp_setup(drv_data);
++ +++  if (is_lpss_ssp(drv_data))
++ +++          lpss_ssp_setup(drv_data);
      
        tasklet_init(&drv_data->pump_transfers, pump_transfers,
                     (unsigned long)drv_data);
@@@@@@@ -1456,7 -1460,7 -1434,7 -1460,7 -1460,7 -1460,7 +1430,7 @@@@@@@ static int pxa2xx_spi_remove(struct pla
        pm_runtime_get_sync(&pdev->dev);
      
        /* Disable the SSP at the peripheral and SOC level */
-- ---  write_SSCR0(0, drv_data->ioaddr);
++ +++  pxa2xx_spi_write(drv_data, SSCR0, 0);
        clk_disable_unprepare(ssp->clk);
      
        /* Release DMA */
@@@@@@@ -1493,7 -1497,7 -1471,7 -1497,7 -1497,7 -1497,7 +1467,7 @@@@@@@ static int pxa2xx_spi_suspend(struct de
        status = spi_master_suspend(drv_data->master);
        if (status != 0)
                return status;
-- ---  write_SSCR0(0, drv_data->ioaddr);
++ +++  pxa2xx_spi_write(drv_data, SSCR0, 0);
      
        if (!pm_runtime_suspended(dev))
                clk_disable_unprepare(ssp->clk);
@@@@@@@ -1514,7 -1518,7 -1492,8 -1518,7 -1518,7 -1518,7 +1488,8 @@@@@@@ static int pxa2xx_spi_resume(struct dev
                clk_prepare_enable(ssp->clk);
      
        /* Restore LPSS private register bits */
-- ---  lpss_ssp_setup(drv_data);
++ +++  if (is_lpss_ssp(drv_data))
++ +++          lpss_ssp_setup(drv_data);
      
        /* Start the queue running */
        status = spi_master_resume(drv_data->master);

diff --combined include/linux/spi/pxa2xx_spi.h
index 5eb56e35cf0d46c0eab9554da2a5802cf28458c5,d5a316550177299fefaee37d6bf3e6a0e3322a8a,46d8fa9426311fa8e1edbd4d2a382eef5ba57e70,d5a316550177299fefaee37d6bf3e6a0e3322a8a,d5a316550177299fefaee37d6bf3e6a0e3322a8a,d5a316550177299fefaee37d6bf3e6a0e3322a8a..6d36dacec4baa1cd88a6bfebd259c4b685a34876
--- 1/include/linux/spi/pxa2xx_spi.h
--- 2/include/linux/spi/pxa2xx_spi.h
--- 3/include/linux/spi/pxa2xx_spi.h
--- 4/include/linux/spi/pxa2xx_spi.h
--- 5/include/linux/spi/pxa2xx_spi.h
--- 6/include/linux/spi/pxa2xx_spi.h
+++ b/include/linux/spi/pxa2xx_spi.h
@@@@@@@ -10,6 -10,10 -10,10 -10,10 -10,10 -10,10 +10,6 @@@@@@@
       * but WITHOUT ANY WARRANTY; without even the implied warranty of
       * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
       * GNU General Public License for more details.
 ----- *
 ----- * You should have received a copy of the GNU General Public License
 ----- * along with this program; if not, write to the Free Software
 ----- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
       */
      #ifndef __linux_pxa2xx_spi_h
      #define __linux_pxa2xx_spi_h
@@@@@@@ -53,7 -57,7 -57,6 -57,7 -57,7 -57,7 +53,6 @@@@@@@ struct pxa2xx_spi_chip 
      #if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)
      
      #include <linux/clk.h>
-- ---#include <mach/dma.h>
      
      extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);