dt-bindings: clock: qcom: Document the X1E80100 Display Clock Controller

Add bindings documentation for the X1E80100 Display Clock Controller.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-2-7fb08c861c7c@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
index 369a0491f8d6ebc0af92e7433d038bf993fcecf5..bad0260764d464b9bf360e50442016a610fa7915 100644 (file)
--- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
@@ -17,12 +17,14 @@ description: |
   See also:
   - include/dt-bindings/clock/qcom,sm8550-dispcc.h
   - include/dt-bindings/clock/qcom,sm8650-dispcc.h
+  - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
 
 properties:
   compatible:
     enum:
       - qcom,sm8550-dispcc
       - qcom,sm8650-dispcc
+      - qcom,x1e80100-dispcc
 
   clocks:
     items:

diff --git a/include/dt-bindings/clock/qcom,x1e80100-dispcc.h b/include/dt-bindings/clock/qcom,x1e80100-dispcc.h
new file mode 100644 (file)
index 0000000..d4a83e4
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,x1e80100-dispcc.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
+#define _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
+
+/* DISP_CC clocks */
+#define DISP_CC_MDSS_ACCU_CLK                                  0
+#define DISP_CC_MDSS_AHB1_CLK                                  1
+#define DISP_CC_MDSS_AHB_CLK                                   2
+#define DISP_CC_MDSS_AHB_CLK_SRC                               3
+#define DISP_CC_MDSS_BYTE0_CLK                                 4
+#define DISP_CC_MDSS_BYTE0_CLK_SRC                             5
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC                         6
+#define DISP_CC_MDSS_BYTE0_INTF_CLK                            7
+#define DISP_CC_MDSS_BYTE1_CLK                                 8
+#define DISP_CC_MDSS_BYTE1_CLK_SRC                             9
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC                         10
+#define DISP_CC_MDSS_BYTE1_INTF_CLK                            11
+#define DISP_CC_MDSS_DPTX0_AUX_CLK                             12
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC                         13
+#define DISP_CC_MDSS_DPTX0_LINK_CLK                            14
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC                                15
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC                    16
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK                       17
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK                          18
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC                      19
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK                          20
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC                      21
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK            22
+#define DISP_CC_MDSS_DPTX1_AUX_CLK                             23
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC                         24
+#define DISP_CC_MDSS_DPTX1_LINK_CLK                            25
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC                                26
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC                    27
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK                       28
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK                          29
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC                      30
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK                          31
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC                      32
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK            33
+#define DISP_CC_MDSS_DPTX2_AUX_CLK                             34
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC                         35
+#define DISP_CC_MDSS_DPTX2_LINK_CLK                            36
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC                                37
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC                    38
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK                       39
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK                          40
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC                      41
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK                          42
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC                      43
+#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK            44
+#define DISP_CC_MDSS_DPTX3_AUX_CLK                             45
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC                         46
+#define DISP_CC_MDSS_DPTX3_LINK_CLK                            47
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC                                48
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC                    49
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK                       50
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK                          51
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC                      52
+#define DISP_CC_MDSS_ESC0_CLK                                  53
+#define DISP_CC_MDSS_ESC0_CLK_SRC                              54
+#define DISP_CC_MDSS_ESC1_CLK                                  55
+#define DISP_CC_MDSS_ESC1_CLK_SRC                              56
+#define DISP_CC_MDSS_MDP1_CLK                                  57
+#define DISP_CC_MDSS_MDP_CLK                                   58
+#define DISP_CC_MDSS_MDP_CLK_SRC                               59
+#define DISP_CC_MDSS_MDP_LUT1_CLK                              60
+#define DISP_CC_MDSS_MDP_LUT_CLK                               61
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK                          62
+#define DISP_CC_MDSS_PCLK0_CLK                                 63
+#define DISP_CC_MDSS_PCLK0_CLK_SRC                             64
+#define DISP_CC_MDSS_PCLK1_CLK                                 65
+#define DISP_CC_MDSS_PCLK1_CLK_SRC                             66
+#define DISP_CC_MDSS_RSCC_AHB_CLK                              67
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK                            68
+#define DISP_CC_MDSS_VSYNC1_CLK                                        69
+#define DISP_CC_MDSS_VSYNC_CLK                                 70
+#define DISP_CC_MDSS_VSYNC_CLK_SRC                             71
+#define DISP_CC_PLL0                                           72
+#define DISP_CC_PLL1                                           73
+#define DISP_CC_SLEEP_CLK                                      74
+#define DISP_CC_SLEEP_CLK_SRC                                  75
+#define DISP_CC_XO_CLK                                         76
+#define DISP_CC_XO_CLK_SRC                                     77
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR                                  0
+#define DISP_CC_MDSS_CORE_INT2_BCR                             1
+#define DISP_CC_MDSS_RSCC_BCR                                  2
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC                                              0
+#define MDSS_INT2_GDSC                                         1
+
+#endif