drm/i915: Require an exact DP link freq match for the DG2 PLL

No idea why the DG2 PLL DP link frequency calculation is allowing
a non-exact match. That makes no sense so get rid of it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-24-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index cc1270978b67e183077d725835f6cc50e2832d8d..b48f42f1832a9bcbdd68d5da7064bd4c76f0c0d6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -629,7 +629,7 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
                return -EINVAL;
 
        for (i = 0; tables[i]; i++) {
-               if (crtc_state->port_clock <= tables[i]->clock) {
+               if (crtc_state->port_clock == tables[i]->clock) {
                        crtc_state->mpllb_state = *tables[i];
                        return 0;
                }