cxl/port: Pre-initialize component register mappings
authorRobert Richter <rrichter@amd.com>
Wed, 18 Oct 2023 17:16:58 +0000 (19:16 +0200)
committerDan Williams <dan.j.williams@intel.com>
Sat, 28 Oct 2023 03:13:37 +0000 (20:13 -0700)
The component registers of a component may not exist and
cxl_setup_comp_regs() will fail for that reason. In another case,
Software may not use and set those registers up. cxl_setup_comp_regs()
is then called with a base address of CXL_RESOURCE_NONE. Both are
valid cases, but the function returns without initializing the
register map.

Now, a missing component register block is not necessarily a reason to
fail (feature is optional or its existence checked later). Change
cxl_setup_comp_regs() to also use components with the component
register block missing. Thus, always initialize struct
cxl_register_map with valid values, set @dev and make @resource
CXL_RESOURCE_NONE.

The change is in preparation of follow-on patches.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20231018171713.1883517-6-rrichter@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/core/port.c

index f6ced15dbf73670d07f861671c8bb87bdf8936d5..252aa3dc96e29aec276cfcdeb3c0e646aa2ae0b5 100644 (file)
@@ -694,16 +694,18 @@ err:
 static int cxl_setup_comp_regs(struct device *host, struct cxl_register_map *map,
                               resource_size_t component_reg_phys)
 {
-       if (component_reg_phys == CXL_RESOURCE_NONE)
-               return 0;
-
        *map = (struct cxl_register_map) {
                .host = host,
-               .reg_type = CXL_REGLOC_RBI_COMPONENT,
+               .reg_type = CXL_REGLOC_RBI_EMPTY,
                .resource = component_reg_phys,
-               .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
        };
 
+       if (component_reg_phys == CXL_RESOURCE_NONE)
+               return 0;
+
+       map->reg_type = CXL_REGLOC_RBI_COMPONENT;
+       map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
+
        return cxl_setup_regs(map);
 }