drm/amd/display: Re-enable DPP/HUBP Power Gating

[Why & How]
Bugs preventing DPP/HUBP power gating have been addressed
so this should be reenabled on dcn314 for sufficient
hardware rev versions

Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 7957ad4d6a34a02015db484d5f4dab6672634e22..a840b008d660305436f80fcd4cf0ff3ed73147e9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -874,8 +874,8 @@ static const struct dc_debug_options debug_defaults_drv = {
        .force_abm_enable = false,
        .timing_trace = false,
        .clock_trace = true,
-       .disable_dpp_power_gate = true,
-       .disable_hubp_power_gate = true,
+       .disable_dpp_power_gate = false,
+       .disable_hubp_power_gate = false,
        .disable_pplib_clock_request = false,
        .pipe_split_policy = MPC_SPLIT_DYNAMIC,
        .force_single_disp_pipe_split = false,
@@ -1883,6 +1883,13 @@ static bool dcn314_resource_construct(
        /* Use pipe context based otg sync logic */
        dc->config.use_pipe_ctx_sync_logic = true;
 
+       /* Disable pipe power gating when unsupported */
+       if (ctx->asic_id.hw_internal_rev == 0x01 ||
+                       ctx->asic_id.hw_internal_rev == 0x80) {
+               dc->debug.disable_dpp_power_gate = true;
+               dc->debug.disable_hubp_power_gate = true;
+       }
+
        /* read VBIOS LTTPR caps */
        {
                if (ctx->dc_bios->funcs->get_lttpr_caps) {