unsigned long flags;
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+ u32 mask = BIT(INTERRUPT_ENABLE_OFF) | BIT(INTERRUPT_MASK_OFF);
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
pin_reg |= BIT(INTERRUPT_MASK_OFF);
writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+ /*
+ * When debounce logic is enabled it takes ~900 us before interrupts
+ * can be enabled. During this "debounce warm up" period the
+ * "INTERRUPT_ENABLE" bit will read as 0. Poll the bit here until it
+ * reads back as 1, signaling that interrupts are now enabled.
+ */
+ while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
+ continue;
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}