drm/i915/display: Calculate crtc clock rate based on PLL parameters

With HDMI monitors we bumped up a case where the crtc clock rate
caused a mismatch on state verification. This was due to
assumption that the SW clock rate from PLL structure would match
the calculated counterpart from HW. This is not necessarily always
the case and therefore we would actually need to recalculate the
clock rate from SW PLL parameters. Then these SW and HW crtc clock
rates can be compared with each other.

The patch recalculates the crtc clock rate for SW state based on
SW PLL parameters and compares the crtc clock rate calculated
from the parameters found from the HW.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240502131716.504616-1-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 8e3b13884bb8dceb159ea2a22c7066276653acaf..89a195917179b232f62d9476f60da4e3e59594e9 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3078,9 +3078,10 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
        const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20;
        bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state);
        bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state);
+       int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state);
        int i;
 
-       I915_STATE_WARN(i915, mpll_hw_state->clock != mpll_sw_state->clock,
+       I915_STATE_WARN(i915, mpll_hw_state->clock != clock,
                        "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)",
                        crtc->base.base.id, crtc->base.name,
                        mpll_sw_state->clock, mpll_hw_state->clock);