clk: mvebu: armada-37xx-periph: Fix the clock gate flag
authorGregory CLEMENT <gregory.clement@free-electrons.com>
Fri, 30 Sep 2016 08:33:59 +0000 (10:33 +0200)
committerStephen Boyd <sboyd@codeaurora.org>
Mon, 17 Oct 2016 22:35:10 +0000 (15:35 -0700)
For the gate part of the peripheral clock setting the bit disables the
clock and clearing it enables the clock. This is not the default behavior
of clk_gate component, so we need to use the CLK_GATE_SET_TO_DISABLE flag.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Fixes: 8ca4746a78ab ("clk: mvebu: Add the peripheral clock driver for Armada 3700")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/mvebu/armada-37xx-periph.c

index d5dfbad4ceabd3d02cf08cf59546cccef6726879..cecb0fdfaef6cd354893f9f4628427c7dee655e5 100644 (file)
@@ -329,6 +329,7 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
                gate->lock = lock;
                gate_ops = gate_hw->init->ops;
                gate->reg = reg + (u64)gate->reg;
+               gate->flags = CLK_GATE_SET_TO_DISABLE;
        }
 
        if (data->rate_hw) {