drivers/perf: Add support for ARMv8.3-SPE

Armv8.3 extends the SPE by adding:
- Alignment field in the Events packet, and filtering on this event
  using PMSEVFR_EL1.
- Support for the Scalable Vector Extension (SVE).

The main additions for SVE are:
- Recording the vector length for SVE operations in the Operation Type
  packet. It is not possible to filter on vector length.
- Incomplete predicate and empty predicate fields in the Events packet,
  and filtering on these events using PMSEVFR_EL1.

Update the check of pmsevfr for empty/partial predicated SVE and
alignment event in SPE driver.

Signed-off-by: Wei Li <liwei391@huawei.com>
Link: https://lore.kernel.org/r/20201203141609.14148-1-liwei391@huawei.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 8b5e7e5c3cc818f5df654a67472ecac5357ebea0..767bb2d47be923527ebab807edfcb756d509c3cc 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -291,7 +291,11 @@
 #define SYS_PMSFCR_EL1_ST_SHIFT                18
 
 #define SYS_PMSEVFR_EL1                        sys_reg(3, 0, 9, 9, 5)
-#define SYS_PMSEVFR_EL1_RES0           0x0000ffff00ff0f55UL
+#define SYS_PMSEVFR_EL1_RES0_8_2       \
+       (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
+        BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
+#define SYS_PMSEVFR_EL1_RES0_8_3       \
+       (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
 
 #define SYS_PMSLATFR_EL1               sys_reg(3, 0, 9, 9, 6)
 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT  0
@@ -844,6 +848,9 @@
 #define ID_AA64DFR0_PMUVER_8_5         0x6
 #define ID_AA64DFR0_PMUVER_IMP_DEF     0xf
 
+#define ID_AA64DFR0_PMSVER_8_2         0x1
+#define ID_AA64DFR0_PMSVER_8_3         0x2
+
 #define ID_DFR0_PERFMON_SHIFT          24
 
 #define ID_DFR0_PERFMON_8_1            0x4

diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
index cc00915ad6d19aa957bbf718f3f7a1e49496c11d..bce9aff9f546f2ea63313eb0817f1af568b5f251 100644 (file)
--- a/drivers/perf/arm_spe_pmu.c
+++ b/drivers/perf/arm_spe_pmu.c
@@ -54,7 +54,7 @@ struct arm_spe_pmu {
        struct hlist_node                       hotplug_node;
 
        int                                     irq; /* PPI */
-
+       u16                                     pmsver;
        u16                                     min_period;
        u16                                     counter_sz;
 
@@ -655,6 +655,18 @@ static irqreturn_t arm_spe_pmu_irq_handler(int irq, void *dev)
        return IRQ_HANDLED;
 }
 
+static u64 arm_spe_pmsevfr_res0(u16 pmsver)
+{
+       switch (pmsver) {
+       case ID_AA64DFR0_PMSVER_8_2:
+               return SYS_PMSEVFR_EL1_RES0_8_2;
+       case ID_AA64DFR0_PMSVER_8_3:
+       /* Return the highest version we support in default */
+       default:
+               return SYS_PMSEVFR_EL1_RES0_8_3;
+       }
+}
+
 /* Perf callbacks */
 static int arm_spe_pmu_event_init(struct perf_event *event)
 {
@@ -670,7 +682,7 @@ static int arm_spe_pmu_event_init(struct perf_event *event)
            !cpumask_test_cpu(event->cpu, &spe_pmu->supported_cpus))
                return -ENOENT;
 
-       if (arm_spe_event_to_pmsevfr(event) & SYS_PMSEVFR_EL1_RES0)
+       if (arm_spe_event_to_pmsevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver))
                return -EOPNOTSUPP;
 
        if (attr->exclude_idle)
@@ -937,6 +949,7 @@ static void __arm_spe_pmu_dev_probe(void *info)
                        fld, smp_processor_id());
                return;
        }
+       spe_pmu->pmsver = (u16)fld;
 
        /* Read PMBIDR first to determine whether or not we have access */
        reg = read_sysreg_s(SYS_PMBIDR_EL1);