drm/i915: pass dev_priv explicitly to DSPOFFSET

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPOFFSET register macro.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c1d487d2c753221144e8fb8f17e5eb2826dba5f2.1716469091.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 36225c2aa1c88cca957a64e178e1cba300066518..2026323d88ac2c4d74251cb0b0f4058325ebeb3d 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -482,7 +482,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
        }
 
        if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-               intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
+               intel_de_write_fw(dev_priv, DSPOFFSET(dev_priv, i9xx_plane),
                                  DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
        } else if (DISPLAY_VER(dev_priv) >= 4) {
                intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane),
@@ -1033,7 +1033,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
        fb->format = drm_format_info(fourcc);
 
        if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-               offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
+               offset = intel_de_read(dev_priv,
+                                      DSPOFFSET(dev_priv, i9xx_plane));
                base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK;
        } else if (DISPLAY_VER(dev_priv) >= 4) {
                if (plane_config->tiling)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index baa3d348c77eb9a760af376ee2c5f1339ca88edc..0930a76ccf3cfabfc7e1e7898d0fb70e91704243 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -78,7 +78,7 @@
 #define   DISP_OFFSET_X(x)             REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
 
 #define _DSPAOFFSET                            0x701A4 /* hsw+ */
-#define DSPOFFSET(plane)                       _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
+#define DSPOFFSET(dev_priv, plane)             _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
 
 #define _DSPASURFLIVE                          0x701AC /* g4x+ */
 #define DSPSURFLIVE(plane)                     _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index a8be80bde2e7927c2063ef55ff74e168ac153460..50dfe1f81b996912e62821a8b8aaddae4c7417db 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -171,7 +171,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(DSPPOS(dev_priv, PIPE_A));
        MMIO_D(DSPSIZE(dev_priv, PIPE_A));
        MMIO_D(DSPSURF(dev_priv, PIPE_A));
-       MMIO_D(DSPOFFSET(PIPE_A));
+       MMIO_D(DSPOFFSET(dev_priv, PIPE_A));
        MMIO_D(DSPSURFLIVE(PIPE_A));
        MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
        MMIO_D(DSPCNTR(dev_priv, PIPE_B));
@@ -180,7 +180,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(DSPPOS(dev_priv, PIPE_B));
        MMIO_D(DSPSIZE(dev_priv, PIPE_B));
        MMIO_D(DSPSURF(dev_priv, PIPE_B));
-       MMIO_D(DSPOFFSET(PIPE_B));
+       MMIO_D(DSPOFFSET(dev_priv, PIPE_B));
        MMIO_D(DSPSURFLIVE(PIPE_B));
        MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));
        MMIO_D(DSPCNTR(dev_priv, PIPE_C));
@@ -189,7 +189,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(DSPPOS(dev_priv, PIPE_C));
        MMIO_D(DSPSIZE(dev_priv, PIPE_C));
        MMIO_D(DSPSURF(dev_priv, PIPE_C));
-       MMIO_D(DSPOFFSET(PIPE_C));
+       MMIO_D(DSPOFFSET(dev_priv, PIPE_C));
        MMIO_D(DSPSURFLIVE(PIPE_C));
        MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY));
        MMIO_D(SPRCTL(PIPE_A));