drm/amd/display: skip program clock when allow seamless boot

[Why]
Driver program dpp clock calculate by pipe split config but hw config is single pipe.

[How]
Skip programming clock when allow seamless boot.
After porgramming pipe config, seamless boot flag will be clear.

Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Wayne Lin <waynelin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index f4374d83662aeb7432a2c8e9ade1ef3644a5094b..931fbb4d61691e4b6b303d97652a3f2d83fa15f9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1206,14 +1206,25 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 {
        const struct dc *dc = link->dc;
        bool ret;
+       bool can_apply_seamless_boot = false;
+       int i;
+
+       for (i = 0; i < dc->current_state->stream_count; i++) {
+               if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
+                       can_apply_seamless_boot = true;
+                       break;
+               }
+       }
 
        /* get out of low power state */
-       clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
+       if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
+               clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
 
        ret = dc_link_detect_helper(link, reason);
 
        /* Go back to power optimized state */
-       clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
+       if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
+               clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
 
        return ret;
 }