}
+void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
+{
+ int ret = 0;
+
+ if (is_support_sw_smu(adev)) {
+ ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_JPEG, enable);
+ if (ret)
+ DRM_ERROR("[SW SMU]: dpm enable jpeg failed, state = %s, ret = %d. \n",
+ enable ? "true" : "false", ret);
+ }
+}
+
int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev)
{
int ret = 0;
void amdgpu_dpm_thermal_work_handler(struct work_struct *work);
void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
+void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
#endif
struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
int r;
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_jpeg(adev, true);
+
/* disable power gating */
r = jpeg_v2_0_disable_power_gating(adev);
if (r)
/* enable power gating */
r = jpeg_v2_0_enable_power_gating(adev);
+ if (r)
+ return r;
- return r;
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_jpeg(adev, false);
+
+ return 0;
}
/**