arm64: dts: rockchip: add PCIe3 bus to rk3588-evb1

Enable PCIe3 support, which is exposed via a PCIe3 connector.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230918141327.131108-3-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
index 23bef9faa690cc67a95dd902d6898a7f5172c199..c3fe58e39e99f1d84904e2f7f47ab08d66dd517e 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
@@ -49,6 +49,26 @@
                vin-supply = <&avcc_1v8_s0>;
        };
 
+       pcie30_avdd0v75: pcie30-avdd0v75-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "pcie30_avdd0v75";
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <750000>;
+               regulator-max-microvolt = <750000>;
+               vin-supply = <&avdd_0v75_s0>;
+       };
+
+       pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "pcie30_avdd1v8";
+               regulator-always-on;
+               regulator-boot-on;
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               vin-supply = <&avcc_1v8_s0>;
+       };
+
        vcc12v_dcin: vcc12v-dcin-regulator {
                compatible = "regulator-fixed";
                regulator-name = "vcc12v_dcin";
@@ -58,6 +78,19 @@
                regulator-max-microvolt = <12000000>;
        };
 
+       vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "vcc3v3_pcie30";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               enable-active-high;
+               gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+               startup-delay-us = <5000>;
+               vin-supply = <&vcc12v_dcin>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&vcc3v3_pcie30_en>;
+       };
+
        vcc5v0_host: vcc5v0-host-regulator {
                compatible = "regulator-fixed";
                regulator-name = "vcc5v0_host";
@@ -194,6 +227,18 @@
        status = "okay";
 };
 
+&pcie30phy {
+       status = "okay";
+};
+
+&pcie3x4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie3_reset>;
+       reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+       vpcie3v3-supply = <&vcc3v3_pcie30>;
+       status = "okay";
+};
+
 &pinctrl {
        rtl8111 {
                rtl8111_isolate: rtl8111-isolate {
@@ -220,6 +265,16 @@
                };
        };
 
+       pcie3 {
+               pcie3_reset: pcie3-reset {
+                       rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+
+               vcc3v3_pcie30_en: vcc3v3-pcie30-en {
+                       rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
        usb {
                vcc5v0_host_en: vcc5v0-host-en {
                        rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;