clk: mediatek: mt8173: Add support for frequency hopping through FHCTL

Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.

This commit brings functional changes only upon addition of
devicetree configuration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230206100105.861720-6-angelogioacchino.delregno@collabora.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
index a56c5845d07a58334148a7263d6d0e471b4d3126..0084203e67ad946bc0cb57f6dc54cf65c46eb7f3 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
+++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c
@@ -9,8 +9,10 @@
 #include <linux/of_address.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include "clk-fhctl.h"
 #include "clk-mtk.h"
 #include "clk-pll.h"
+#include "clk-pllfh.h"
 
 #define REGOFF_REF2USB         0x8
 #define REGOFF_HDMI_REF                0x40
@@ -77,6 +79,58 @@ static const struct mtk_pll_data plls[] = {
        PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
 };
 
+enum fh_pll_id {
+       FH_ARMCA7PLL,
+       FH_ARMCA15PLL,
+       FH_MAINPLL,
+       FH_MPLL,
+       FH_MSDCPLL,
+       FH_MMPLL,
+       FH_VENCPLL,
+       FH_TVDPLL,
+       FH_VCODECPLL,
+       FH_LVDSPLL,
+       FH_MSDC2PLL,
+       FH_NR_FH,
+};
+
+#define FH(_pllid, _fhid, _offset) {                                   \
+               .data = {                                               \
+                       .pll_id = _pllid,                               \
+                       .fh_id = _fhid,                                 \
+                       .fh_ver = FHCTL_PLLFH_V1,                       \
+                       .fhx_offset = _offset,                          \
+                       .dds_mask = GENMASK(21, 0),                     \
+                       .slope0_value = 0x6003c97,                      \
+                       .slope1_value = 0x6003c97,                      \
+                       .sfstrx_en = BIT(2),                            \
+                       .frddsx_en = BIT(1),                            \
+                       .fhctlx_en = BIT(0),                            \
+                       .tgl_org = BIT(31),                             \
+                       .dvfs_tri = BIT(31),                            \
+                       .pcwchg = BIT(31),                              \
+                       .dt_val = 0x0,                                  \
+                       .df_val = 0x9,                                  \
+                       .updnlmt_shft = 16,                             \
+                       .msk_frddsx_dys = GENMASK(23, 20),              \
+                       .msk_frddsx_dts = GENMASK(19, 16),              \
+               },                                                      \
+       }
+
+static struct mtk_pllfh_data pllfhs[] = {
+       FH(CLK_APMIXED_ARMCA7PLL, FH_ARMCA7PLL, 0x38),
+       FH(CLK_APMIXED_ARMCA15PLL, FH_ARMCA15PLL, 0x4c),
+       FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60),
+       FH(CLK_APMIXED_MPLL, FH_MPLL, 0x74),
+       FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88),
+       FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c),
+       FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0),
+       FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4),
+       FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8),
+       FH(CLK_APMIXED_LVDSPLL, FH_LVDSPLL, 0xec),
+       FH(CLK_APMIXED_MSDCPLL2, FH_MSDC2PLL, 0x100),
+};
+
 static const struct of_device_id of_match_clk_mt8173_apmixed[] = {
        { .compatible = "mediatek,mt8173-apmixedsys" },
        { /* sentinel */ }
@@ -84,6 +138,7 @@ static const struct of_device_id of_match_clk_mt8173_apmixed[] = {
 
 static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
 {
+       const u8 *fhctl_node = "mediatek,mt8173-fhctl";
        struct device_node *node = pdev->dev.of_node;
        struct clk_hw_onecell_data *clk_data;
        void __iomem *base;
@@ -98,7 +153,9 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
        if (IS_ERR_OR_NULL(clk_data))
                return -ENOMEM;
 
-       r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+       fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
+       r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+                                   pllfhs, ARRAY_SIZE(pllfhs), clk_data);
        if (r)
                goto free_clk_data;
 
@@ -124,7 +181,8 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
 unregister_ref2usb:
        mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
 unregister_plls:
-       mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+       mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
+                                 ARRAY_SIZE(pllfhs), clk_data);
 free_clk_data:
        mtk_free_clk_data(clk_data);
        return r;
@@ -137,7 +195,8 @@ static int clk_mt8173_apmixed_remove(struct platform_device *pdev)
 
        of_clk_del_provider(node);
        mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]);
-       mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+       mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
+                                 ARRAY_SIZE(pllfhs), clk_data);
        mtk_free_clk_data(clk_data);
 
        return 0;