drm/amdgpu: add VCN2.0 decode ring test
authorLeo Liu <leo.liu@amd.com>
Wed, 17 Oct 2018 18:33:48 +0000 (14:33 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 21 Jun 2019 23:58:22 +0000 (18:58 -0500)
Add internal register offset for registers involving in ring tests

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

index 8ece427b6019b147bbf29f52c244a1be70b91538..5dbd975bac09545b6e5083250ca1d9fa06f5d5d0 100644 (file)
@@ -312,17 +312,15 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
        unsigned i;
        int r;
 
-       WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD);
+       WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD);
        r = amdgpu_ring_alloc(ring, 3);
        if (r)
                return r;
-
-       amdgpu_ring_write(ring,
-               PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0));
+       amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
        amdgpu_ring_write(ring, 0xDEADBEEF);
        amdgpu_ring_commit(ring);
        for (i = 0; i < adev->usec_timeout; i++) {
-               tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
+               tmp = RREG32(adev->vcn.external.scratch9);
                if (tmp == 0xDEADBEEF)
                        break;
                DRM_UDELAY(1);
index a1ee19251aae654005ebdbc26c9a9512c7457f98..b80fc139eb7b4bfac577e8dbd51da25a0b470164 100644 (file)
@@ -87,6 +87,10 @@ struct dpg_pause_state {
        enum internal_dpg_state jpeg;
 };
 
+struct amdgpu_vcn_reg{
+       unsigned        scratch9;
+};
+
 struct amdgpu_vcn {
        struct amdgpu_bo        *vcpu_bo;
        void                    *cpu_addr;
@@ -102,6 +106,7 @@ struct amdgpu_vcn {
        unsigned                num_enc_rings;
        enum amd_powergating_state cur_state;
        struct dpg_pause_state pause_state;
+       struct amdgpu_vcn_reg   internal, external;
        int (*pause_dpg_mode)(struct amdgpu_device *adev,
                struct dpg_pause_state *new_state);
 };
index bb47f5b24be50003906c997340e0571350ad0227..bab900653a0bda3aed4a3c24e5b96304d9a9fd88 100644 (file)
@@ -128,6 +128,9 @@ static int vcn_v1_0_sw_init(void *handle)
        if (r)
                return r;
 
+       adev->vcn.internal.scratch9 = adev->vcn.external.scratch9 =
+               SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
+
        for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
                ring = &adev->vcn.ring_enc[i];
                sprintf(ring->name, "vcn_enc%d", i);