clk: sunxi-ng: mp: introduce dual-divider clock

The Allwinner A523 SoC introduces some new MP-style mod clock, where the
second "P" divider is an actual numerical divider value, and not the
numbers of bits to shift (1..32 instead of 1,2,4,8).
The rest of the clock is the same as the existing MP clock, so enhance the
existing code to accommodate for this.

Introduce the new CCU feature bit CCU_FEATURE_DUAL_DIV to mark an MP
clock as having two dividers, and change the dividing and encoding code
to differentiate the two cases.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Link: https://patch.msgid.link/20250307002628.10684-2-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index dd330426a6e5f39825606f345b231ce4186d0a7b..50fd268329671c007c583bc22234e38de38521f7 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -19,6 +19,7 @@
 #define CCU_FEATURE_SIGMA_DELTA_MOD    BIT(7)
 #define CCU_FEATURE_KEY_FIELD          BIT(8)
 #define CCU_FEATURE_CLOSEST_RATE       BIT(9)
+#define CCU_FEATURE_DUAL_DIV           BIT(10)
 
 /* MMC timing mode switch bit */
 #define CCU_MMC_NEW_TIMING_MODE                BIT(30)

diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
index 2bb8987ddcc20500e74b921444a9115fa6d57c34..354c981943b6f806e0c3534e31775e31a9ceca2b 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu_mp.c
+++ b/drivers/clk/sunxi-ng/ccu_mp.c
@@ -10,15 +10,23 @@
 #include "ccu_gate.h"
 #include "ccu_mp.h"
 
+static unsigned int next_div(unsigned int div, bool shift)
+{
+       if (shift)
+               return div << 1;
+       return div + 1;
+}
+
 static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate,
                                      unsigned int max_m, unsigned int max_p,
+                                     bool shift,
                                      unsigned int *m, unsigned int *p)
 {
        unsigned long best_rate = 0;
        unsigned int best_m = 0, best_p = 0;
        unsigned int _m, _p;
 
-       for (_p = 1; _p <= max_p; _p <<= 1) {
+       for (_p = 1; _p <= max_p; _p = next_div(_p, shift)) {
                for (_m = 1; _m <= max_m; _m++) {
                        unsigned long tmp_rate = parent / _p / _m;
 
@@ -43,7 +51,8 @@ static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
                                                      unsigned long *parent,
                                                      unsigned long rate,
                                                      unsigned int max_m,
-                                                     unsigned int max_p)
+                                                     unsigned int max_p,
+                                                     bool shift)
 {
        unsigned long parent_rate_saved;
        unsigned long parent_rate, now;
@@ -60,7 +69,7 @@ static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
        maxdiv = max_m * max_p;
        maxdiv = min(ULONG_MAX / rate, maxdiv);
 
-       for (_p = 1; _p <= max_p; _p <<= 1) {
+       for (_p = 1; _p <= max_p; _p = next_div(_p, shift)) {
                for (_m = 1; _m <= max_m; _m++) {
                        div = _m * _p;
 
@@ -103,18 +112,26 @@ static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
        struct ccu_mp *cmp = data;
        unsigned int max_m, max_p;
        unsigned int m, p;
+       bool shift = true;
 
        if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
                rate *= cmp->fixed_post_div;
 
+       if (cmp->common.features & CCU_FEATURE_DUAL_DIV)
+               shift = false;
+
        max_m = cmp->m.max ?: 1 << cmp->m.width;
-       max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
+       if (shift)
+               max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
+       else
+               max_p = cmp->p.max ?: 1 << cmp->p.width;
 
        if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) {
-               rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
+               rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, shift,
+                                       &m, &p);
        } else {
                rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
-                                                       max_m, max_p);
+                                                       max_m, max_p, shift);
        }
 
        if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
@@ -167,7 +184,11 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
        p = reg >> cmp->p.shift;
        p &= (1 << cmp->p.width) - 1;
 
-       rate = (parent_rate >> p) / m;
+       if (cmp->common.features & CCU_FEATURE_DUAL_DIV)
+               rate = (parent_rate / p) / m;
+       else
+               rate = (parent_rate >> p) / m;
+
        if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
                rate /= cmp->fixed_post_div;
 
@@ -190,20 +211,27 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
        unsigned long flags;
        unsigned int max_m, max_p;
        unsigned int m, p;
+       bool shift = true;
        u32 reg;
 
+       if (cmp->common.features & CCU_FEATURE_DUAL_DIV)
+               shift = false;
+
        /* Adjust parent_rate according to pre-dividers */
        parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,
                                                  parent_rate);
 
        max_m = cmp->m.max ?: 1 << cmp->m.width;
-       max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
+       if (shift)
+               max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
+       else
+               max_p = cmp->p.max ?: 1 << cmp->p.width;
 
        /* Adjust target rate according to post-dividers */
        if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
                rate = rate * cmp->fixed_post_div;
 
-       ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
+       ccu_mp_find_best(parent_rate, rate, max_m, max_p, shift, &m, &p);
 
        spin_lock_irqsave(cmp->common.lock, flags);
 
@@ -211,7 +239,10 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
        reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
        reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
        reg |= (m - cmp->m.offset) << cmp->m.shift;
-       reg |= ilog2(p) << cmp->p.shift;
+       if (shift)
+               reg |= ilog2(p) << cmp->p.shift;
+       else
+               reg |= (p - cmp->p.offset) << cmp->p.shift;
 
        writel(reg, cmp->common.base + cmp->common.reg);