drm/exynos: fimd: fix alpha setting for XR24 pixel format
authorGustavo Padovan <gustavo.padovan@collabora.co.uk>
Wed, 1 Apr 2015 16:02:05 +0000 (13:02 -0300)
committerInki Dae <inki.dae@samsung.com>
Mon, 13 Apr 2015 02:39:39 +0000 (11:39 +0900)
XR24 planes were not shown properly, so now set the right registers
to correctly enable displaying these planes.

It also moves the alpha register settings to fimd_win_set_pixfmt()
to keep all pixel format stuff together.

v2: remove leftover var alpha

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
drivers/gpu/drm/exynos/exynos_drm_fimd.c
include/video/samsung_fimd.h

index 33a10ce967eacdfbcbc679a8645baae4515b4f1b..6f51d3d7ef6f35d1a7f788956136a7f6ea000835 100644 (file)
@@ -54,6 +54,9 @@
 /* size control register for hardware windows 1 ~ 2. */
 #define VIDOSD_D(win)          (VIDOSD_BASE + 0x0C + (win) * 16)
 
+#define VIDWnALPHA0(win)       (VIDW_ALPHA + 0x00 + (win) * 8)
+#define VIDWnALPHA1(win)       (VIDW_ALPHA + 0x04 + (win) * 8)
+
 #define VIDWx_BUF_START(win, buf)      (VIDW_BUF_START(buf) + (win) * 8)
 #define VIDWx_BUF_END(win, buf)                (VIDW_BUF_END(buf) + (win) * 8)
 #define VIDWx_BUF_SIZE(win, buf)       (VIDW_BUF_SIZE(buf) + (win) * 4)
@@ -620,6 +623,24 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
        }
 
        writel(val, ctx->regs + WINCON(win));
+
+       /* hardware window 0 doesn't support alpha channel. */
+       if (win != 0) {
+               /* OSD alpha */
+               val = VIDISD14C_ALPHA0_R(0xf) |
+                       VIDISD14C_ALPHA0_G(0xf) |
+                       VIDISD14C_ALPHA0_B(0xf) |
+                       VIDISD14C_ALPHA1_R(0xf) |
+                       VIDISD14C_ALPHA1_G(0xf) |
+                       VIDISD14C_ALPHA1_B(0xf);
+
+               writel(val, ctx->regs + VIDOSD_C(win));
+
+               val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
+                       VIDW_ALPHA_G(0xf);
+               writel(val, ctx->regs + VIDWnALPHA0(win));
+               writel(val, ctx->regs + VIDWnALPHA1(win));
+       }
 }
 
 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
@@ -667,7 +688,7 @@ static void fimd_win_commit(struct exynos_drm_crtc *crtc, int zpos)
        struct fimd_context *ctx = crtc->ctx;
        struct fimd_win_data *win_data;
        int win = zpos;
-       unsigned long val, alpha, size;
+       unsigned long val, size;
        unsigned int last_x;
        unsigned int last_y;
 
@@ -744,16 +765,6 @@ static void fimd_win_commit(struct exynos_drm_crtc *crtc, int zpos)
        DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
                        win_data->offset_x, win_data->offset_y, last_x, last_y);
 
-       /* hardware window 0 doesn't support alpha channel. */
-       if (win != 0) {
-               /* OSD alpha */
-               alpha = VIDISD14C_ALPHA1_R(0xf) |
-                       VIDISD14C_ALPHA1_G(0xf) |
-                       VIDISD14C_ALPHA1_B(0xf);
-
-               writel(alpha, ctx->regs + VIDOSD_C(win));
-       }
-
        /* OSD size */
        if (win != 3 && win != 4) {
                u32 offset = VIDOSD_D(win);
index a20e4a3a8b15cb5deaaa7f6534403ccb751d4284..513242827b07a24ebb25fa5af800cc302c04eb89 100644 (file)
 #define VIDISD14C_ALPHA1_B_LIMIT               0xf
 #define VIDISD14C_ALPHA1_B(_x)                 ((_x) << 0)
 
+#define VIDW_ALPHA                             0x021c
+#define VIDW_ALPHA_R(_x)                       ((_x) << 16)
+#define VIDW_ALPHA_G(_x)                       ((_x) << 8)
+#define VIDW_ALPHA_B(_x)                       ((_x) << 0)
+
 /* Video buffer addresses */
 #define VIDW_BUF_START(_buff)                  (0xA0 + ((_buff) * 8))
 #define VIDW_BUF_START1(_buff)                 (0xA4 + ((_buff) * 8))