scsi: ufs: exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option
authorPeter Griffin <peter.griffin@linaro.org>
Fri, 26 Apr 2024 12:20:00 +0000 (13:20 +0100)
committerMartin K. Petersen <martin.petersen@oracle.com>
Tue, 7 May 2024 01:34:37 +0000 (21:34 -0400)
This option is intended to be set on platforms whose ufspr registers are
only accessible via smc call (such as gs101).

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240426122004.2249178-3-peter.griffin@linaro.org
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
drivers/ufs/host/ufs-exynos.c
drivers/ufs/host/ufs-exynos.h

index 734d40f99e31e6baa53e5256039b5429a62f2ef4..0219a5806619ee9627af7269c4a0d2884f4010be 100644 (file)
@@ -1186,7 +1186,10 @@ static int exynos_ufs_init(struct ufs_hba *hba)
        if (ret)
                goto out;
        exynos_ufs_specify_phy_time_attr(ufs);
-       exynos_ufs_config_smu(ufs);
+       if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE))
+               exynos_ufs_config_smu(ufs);
+
+       hba->host->dma_alignment = SZ_4K - 1;
        return 0;
 
 out:
index a4bd6646d7f13f0a7d867cded667501334c2dbb3..0fc21b6bbfcde7418da7731fe7b69f355e53fa8e 100644 (file)
@@ -221,6 +221,7 @@ struct exynos_ufs {
 #define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX       BIT(3)
 #define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER    BIT(4)
 #define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR    BIT(5)
+#define EXYNOS_UFS_OPT_UFSPR_SECURE            BIT(6)
 };
 
 #define for_each_ufs_rx_lane(ufs, i) \