riscv: hwprobe: export Zicntr and Zihpm extensions

Export Zicntr and Zihpm ISA extensions through the hwprobe syscall.

[ alex: Fix hwprobe numbering ]

Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
Acked-by: Jesse Taube <jesse@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240913051324.8176-1-mikisabate@gmail.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index f273ea15a8e83617ba25dda6bc58b97c2e56173d..35a979dd164a6b5ed3c97c800ba8629bd5c9fd6d 100644 (file)
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -183,6 +183,9 @@ The following keys are defined:
        defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
        from commit 5059e0ca641c ("update to ratified").
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0
+       is supported as defined in the RISC-V ISA manual.
+
   * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as
        defined in the RISC-V Integer Conditional (Zicond) operations extension
        manual starting from commit 95cf1f9 ("Add changes requested by Ved
@@ -192,6 +195,9 @@ The following keys are defined:
        supported as defined in the RISC-V ISA manual starting from commit
        d8ab5c78c207 ("Zihintpause is ratified").
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0
+       is supported as defined in the RISC-V ISA manual.
+
   * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
     supported, as defined by version 1.0 of the RISC-V Vector extension manual.
 

diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index c3c1cc951cb9426f923de88939949d613657cd50..8cac35cb19d8b154ba117ca924f77e4c4b46c0ed 100644 (file)
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -73,6 +73,8 @@ struct riscv_hwprobe {
 #define                RISCV_HWPROBE_EXT_ZCMOP         (1ULL << 47)
 #define                RISCV_HWPROBE_EXT_ZAWRS         (1ULL << 48)
 #define                RISCV_HWPROBE_EXT_SUPM          (1ULL << 49)
+#define                RISCV_HWPROBE_EXT_ZICNTR        (1ULL << 50)
+#define                RISCV_HWPROBE_EXT_ZIHPM         (1ULL << 51)
 #define RISCV_HWPROBE_KEY_CPUPERF_0    5
 #define                RISCV_HWPROBE_MISALIGNED_UNKNOWN        (0 << 0)
 #define                RISCV_HWPROBE_MISALIGNED_EMULATED       (1 << 0)

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index bcd3b816306c22df62f60ad044f4ae58f7dad4d1..b35cce0b57aec7677539cd1be113ef2bbfed4f4a 100644 (file)
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -108,9 +108,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
                EXT_KEY(ZCB);
                EXT_KEY(ZCMOP);
                EXT_KEY(ZICBOZ);
+               EXT_KEY(ZICNTR);
                EXT_KEY(ZICOND);
                EXT_KEY(ZIHINTNTL);
                EXT_KEY(ZIHINTPAUSE);
+               EXT_KEY(ZIHPM);
                EXT_KEY(ZIMOP);
                EXT_KEY(ZKND);
                EXT_KEY(ZKNE);