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powerpc/pmem: Avoid the barrier in flush routines
author
Aneesh Kumar K.V
<aneesh.kumar@linux.ibm.com>
Wed, 1 Jul 2020 07:22:34 +0000
(12:52 +0530)
committer
Michael Ellerman
<mpe@ellerman.id.au>
Thu, 16 Jul 2020 03:00:23 +0000
(13:00 +1000)
nvdimm expect the flush routines to just mark the cache clean. The barrier
that mark the store globally visible is done in nvdimm_flush().
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link:
https://lore.kernel.org/r/20200701072235.223558-7-aneesh.kumar@linux.ibm.com
arch/powerpc/lib/pmem.c
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diff --git
a/arch/powerpc/lib/pmem.c
b/arch/powerpc/lib/pmem.c
index 5a61aaeb69302b1568635a3b45e2636acc64e75a..21210fa676e50da6610ef93a1b1502e910511931 100644
(file)
--- a/
arch/powerpc/lib/pmem.c
+++ b/
arch/powerpc/lib/pmem.c
@@
-19,9
+19,6
@@
static inline void __clean_pmem_range(unsigned long start, unsigned long stop)
for (i = 0; i < size >> shift; i++, addr += bytes)
asm volatile(PPC_DCBSTPS(%0, %1): :"i"(0), "r"(addr): "memory");
-
-
- asm volatile(PPC_PHWSYNC ::: "memory");
}
static inline void __flush_pmem_range(unsigned long start, unsigned long stop)
@@
-34,9
+31,6
@@
static inline void __flush_pmem_range(unsigned long start, unsigned long stop)
for (i = 0; i < size >> shift; i++, addr += bytes)
asm volatile(PPC_DCBFPS(%0, %1): :"i"(0), "r"(addr): "memory");
-
-
- asm volatile(PPC_PHWSYNC ::: "memory");
}
static inline void clean_pmem_range(unsigned long start, unsigned long stop)