arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties
authorKrishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Fri, 28 Mar 2025 10:28:29 +0000 (15:58 +0530)
committerBjorn Andersson <andersson@kernel.org>
Mon, 19 May 2025 20:33:50 +0000 (15:33 -0500)
Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data
rates used in lane equalization procedure.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20250328-preset_v6-v9-1-22cfa0490518@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arch/arm64/boot/dts/qcom/x1e80100.dtsi

index 2577a0f4dd7162e077a6e5f9084505e330b6a22e..1f0e50b0e6a1500ee3bf2fe82a9071a3e6bb66c6 100644 (file)
                        phys = <&pcie3_phy>;
                        phy-names = "pciephy";
 
+                       eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
+                                                    0x5555 0x5555 0x5555 0x5555>;
+                       eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
+
                        operating-points-v2 = <&pcie3_opp_table>;
 
                        status = "disabled";
                        phys = <&pcie6a_phy>;
                        phy-names = "pciephy";
 
+                       eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
+                       eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
+
                        status = "disabled";
                };
 
                        phys = <&pcie5_phy>;
                        phy-names = "pciephy";
 
+                       eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
+
                        status = "disabled";
                };
 
                        phys = <&pcie4_phy>;
                        phy-names = "pciephy";
 
+                       eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
+
                        status = "disabled";
 
                        pcie4_port0: pcie@0 {