[PATCH] ppc64: SMU based macs cpufreq support
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Mon, 7 Nov 2005 03:27:33 +0000 (14:27 +1100)
committerPaul Mackerras <paulus@samba.org>
Tue, 8 Nov 2005 00:17:34 +0000 (11:17 +1100)
CPU freq support using 970FX powertune facility for iMac G5 and SMU
based single CPU desktop.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
12 files changed:
arch/powerpc/Kconfig
arch/powerpc/kernel/misc_64.S
arch/powerpc/platforms/powermac/Makefile
arch/powerpc/platforms/powermac/cpufreq.c [deleted file]
arch/powerpc/platforms/powermac/cpufreq_32.c [new file with mode: 0644]
arch/powerpc/platforms/powermac/cpufreq_64.c [new file with mode: 0644]
arch/powerpc/platforms/powermac/setup.c
arch/ppc64/Kconfig
arch/ppc64/kernel/misc.S
drivers/macintosh/smu.c
include/asm-powerpc/reg.h
include/asm-powerpc/smu.h

index 6ffae2d2b3fa655ad46dcde5cfac90996cde7bc0..3ac9195dab35cbf483e698c8e0ac506549fa2d7c 100644 (file)
@@ -404,6 +404,14 @@ config CPU_FREQ_PMAC
          this currently includes some models of iBook & Titanium
          PowerBook.
 
+config CPU_FREQ_PMAC64
+       bool "Support for some Apple G5s"
+       depends on CPU_FREQ && PMAC_SMU && PPC64
+       select CPU_FREQ_TABLE
+       help
+         This adds support for frequency switching on Apple iMac G5,
+         and some of the more recent desktop G5 machines as well.
+
 config PPC601_SYNC_FIX
        bool "Workarounds for PPC601 bugs"
        depends on 6xx && (PPC_PREP || PPC_PMAC)
index b3e95ff0dba0a63116d6e06f375d56c138dec85b..ae1433da09b27ea4cd76f0013616a35d38560855 100644 (file)
@@ -603,6 +603,76 @@ _GLOBAL(real_writeb)
        blr
 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
 
+/*
+ * SCOM access functions for 970 (FX only for now)
+ *
+ * unsigned long scom970_read(unsigned int address);
+ * void scom970_write(unsigned int address, unsigned long value);
+ *
+ * The address passed in is the 24 bits register address. This code
+ * is 970 specific and will not check the status bits, so you should
+ * know what you are doing.
+ */
+_GLOBAL(scom970_read)
+       /* interrupts off */
+       mfmsr   r4
+       ori     r0,r4,MSR_EE
+       xori    r0,r0,MSR_EE
+       mtmsrd  r0,1
+
+       /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
+        * (including parity). On current CPUs they must be 0'd,
+        * and finally or in RW bit
+        */
+       rlwinm  r3,r3,8,0,15
+       ori     r3,r3,0x8000
+
+       /* do the actual scom read */
+       sync
+       mtspr   SPRN_SCOMC,r3
+       isync
+       mfspr   r3,SPRN_SCOMD
+       isync
+       mfspr   r0,SPRN_SCOMC
+       isync
+
+       /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
+        * that's the best we can do). Not implemented yet as we don't use
+        * the scom on any of the bogus CPUs yet, but may have to be done
+        * ultimately
+        */
+
+       /* restore interrupts */
+       mtmsrd  r4,1
+       blr
+
+
+_GLOBAL(scom970_write)
+       /* interrupts off */
+       mfmsr   r5
+       ori     r0,r5,MSR_EE
+       xori    r0,r0,MSR_EE
+       mtmsrd  r0,1
+
+       /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
+        * (including parity). On current CPUs they must be 0'd.
+        */
+
+       rlwinm  r3,r3,8,0,15
+
+       sync
+       mtspr   SPRN_SCOMD,r4      /* write data */
+       isync
+       mtspr   SPRN_SCOMC,r3      /* write command */
+       isync
+       mfspr   3,SPRN_SCOMC
+       isync
+
+       /* restore interrupts */
+       mtmsrd  r5,1
+       blr
+
+
 /*
  * Create a kernel thread
  *   kernel_thread(fn, arg, flags)
index 4369676f1d541d416665a4e1d165150ed7566f78..c9df44fcf5710f0ea558b39df6cb945efd090011 100644 (file)
@@ -1,7 +1,8 @@
 obj-y                          += pic.o setup.o time.o feature.o pci.o \
                                   sleep.o low_i2c.o cache.o
 obj-$(CONFIG_PMAC_BACKLIGHT)   += backlight.o
-obj-$(CONFIG_CPU_FREQ_PMAC)    += cpufreq.o
+obj-$(CONFIG_CPU_FREQ_PMAC)    += cpufreq_32.o
+obj-$(CONFIG_CPU_FREQ_PMAC64)  += cpufreq_64.o
 obj-$(CONFIG_NVRAM)            += nvram.o
 # ppc64 pmac doesn't define CONFIG_NVRAM but needs nvram stuff
 obj-$(CONFIG_PPC64)            += nvram.o
diff --git a/arch/powerpc/platforms/powermac/cpufreq.c b/arch/powerpc/platforms/powermac/cpufreq.c
deleted file mode 100644 (file)
index c47f8b6..0000000
+++ /dev/null
@@ -1,726 +0,0 @@
-/*
- *  arch/ppc/platforms/pmac_cpufreq.c
- *
- *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
- *  Copyright (C) 2004        John Steele Scott <toojays@toojays.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * TODO: Need a big cleanup here. Basically, we need to have different
- * cpufreq_driver structures for the different type of HW instead of the
- * current mess. We also need to better deal with the detection of the
- * type of machine.
- *
- */
-
-#include <linux/config.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/sched.h>
-#include <linux/adb.h>
-#include <linux/pmu.h>
-#include <linux/slab.h>
-#include <linux/cpufreq.h>
-#include <linux/init.h>
-#include <linux/sysdev.h>
-#include <linux/i2c.h>
-#include <linux/hardirq.h>
-#include <asm/prom.h>
-#include <asm/machdep.h>
-#include <asm/irq.h>
-#include <asm/pmac_feature.h>
-#include <asm/mmu_context.h>
-#include <asm/sections.h>
-#include <asm/cputable.h>
-#include <asm/time.h>
-#include <asm/system.h>
-#include <asm/mpic.h>
-#include <asm/keylargo.h>
-
-/* WARNING !!! This will cause calibrate_delay() to be called,
- * but this is an __init function ! So you MUST go edit
- * init/main.c to make it non-init before enabling DEBUG_FREQ
- */
-#undef DEBUG_FREQ
-
-/*
- * There is a problem with the core cpufreq code on SMP kernels,
- * it won't recalculate the Bogomips properly
- */
-#ifdef CONFIG_SMP
-#warning "WARNING, CPUFREQ not recommended on SMP kernels"
-#endif
-
-extern void low_choose_7447a_dfs(int dfs);
-extern void low_choose_750fx_pll(int pll);
-extern void low_sleep_handler(void);
-
-/*
- * Currently, PowerMac cpufreq supports only high & low frequencies
- * that are set by the firmware
- */
-static unsigned int low_freq;
-static unsigned int hi_freq;
-static unsigned int cur_freq;
-static unsigned int sleep_freq;
-
-/*
- * Different models uses different mecanisms to switch the frequency
- */
-static int (*set_speed_proc)(int low_speed);
-static unsigned int (*get_speed_proc)(void);
-
-/*
- * Some definitions used by the various speedprocs
- */
-static u32 voltage_gpio;
-static u32 frequency_gpio;
-static u32 slew_done_gpio;
-static int no_schedule;
-static int has_cpu_l2lve;
-static int is_pmu_based;
-
-/* There are only two frequency states for each processor. Values
- * are in kHz for the time being.
- */
-#define CPUFREQ_HIGH                  0
-#define CPUFREQ_LOW                   1
-
-static struct cpufreq_frequency_table pmac_cpu_freqs[] = {
-       {CPUFREQ_HIGH,          0},
-       {CPUFREQ_LOW,           0},
-       {0,                     CPUFREQ_TABLE_END},
-};
-
-static struct freq_attr* pmac_cpu_freqs_attr[] = {
-       &cpufreq_freq_attr_scaling_available_freqs,
-       NULL,
-};
-
-static inline void local_delay(unsigned long ms)
-{
-       if (no_schedule)
-               mdelay(ms);
-       else
-               msleep(ms);
-}
-
-#ifdef DEBUG_FREQ
-static inline void debug_calc_bogomips(void)
-{
-       /* This will cause a recalc of bogomips and display the
-        * result. We backup/restore the value to avoid affecting the
-        * core cpufreq framework's own calculation.
-        */
-       extern void calibrate_delay(void);
-
-       unsigned long save_lpj = loops_per_jiffy;
-       calibrate_delay();
-       loops_per_jiffy = save_lpj;
-}
-#endif /* DEBUG_FREQ */
-
-/* Switch CPU speed under 750FX CPU control
- */
-static int cpu_750fx_cpu_speed(int low_speed)
-{
-       u32 hid2;
-
-       if (low_speed == 0) {
-               /* ramping up, set voltage first */
-               pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
-               /* Make sure we sleep for at least 1ms */
-               local_delay(10);
-
-               /* tweak L2 for high voltage */
-               if (has_cpu_l2lve) {
-                       hid2 = mfspr(SPRN_HID2);
-                       hid2 &= ~0x2000;
-                       mtspr(SPRN_HID2, hid2);
-               }
-       }
-#ifdef CONFIG_6xx
-       low_choose_750fx_pll(low_speed);
-#endif
-       if (low_speed == 1) {
-               /* tweak L2 for low voltage */
-               if (has_cpu_l2lve) {
-                       hid2 = mfspr(SPRN_HID2);
-                       hid2 |= 0x2000;
-                       mtspr(SPRN_HID2, hid2);
-               }
-
-               /* ramping down, set voltage last */
-               pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
-               local_delay(10);
-       }
-
-       return 0;
-}
-
-static unsigned int cpu_750fx_get_cpu_speed(void)
-{
-       if (mfspr(SPRN_HID1) & HID1_PS)
-               return low_freq;
-       else
-               return hi_freq;
-}
-
-/* Switch CPU speed using DFS */
-static int dfs_set_cpu_speed(int low_speed)
-{
-       if (low_speed == 0) {
-               /* ramping up, set voltage first */
-               pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
-               /* Make sure we sleep for at least 1ms */
-               local_delay(1);
-       }
-
-       /* set frequency */
-#ifdef CONFIG_6xx
-       low_choose_7447a_dfs(low_speed);
-#endif
-       udelay(100);
-
-       if (low_speed == 1) {
-               /* ramping down, set voltage last */
-               pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
-               local_delay(1);
-       }
-
-       return 0;
-}
-
-static unsigned int dfs_get_cpu_speed(void)
-{
-       if (mfspr(SPRN_HID1) & HID1_DFS)
-               return low_freq;
-       else
-               return hi_freq;
-}
-
-
-/* Switch CPU speed using slewing GPIOs
- */
-static int gpios_set_cpu_speed(int low_speed)
-{
-       int gpio, timeout = 0;
-
-       /* If ramping up, set voltage first */
-       if (low_speed == 0) {
-               pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
-               /* Delay is way too big but it's ok, we schedule */
-               local_delay(10);
-       }
-
-       /* Set frequency */
-       gpio =  pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
-       if (low_speed == ((gpio & 0x01) == 0))
-               goto skip;
-
-       pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, frequency_gpio,
-                         low_speed ? 0x04 : 0x05);
-       udelay(200);
-       do {
-               if (++timeout > 100)
-                       break;
-               local_delay(1);
-               gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, slew_done_gpio, 0);
-       } while((gpio & 0x02) == 0);
- skip:
-       /* If ramping down, set voltage last */
-       if (low_speed == 1) {
-               pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
-               /* Delay is way too big but it's ok, we schedule */
-               local_delay(10);
-       }
-
-#ifdef DEBUG_FREQ
-       debug_calc_bogomips();
-#endif
-
-       return 0;
-}
-
-/* Switch CPU speed under PMU control
- */
-static int pmu_set_cpu_speed(int low_speed)
-{
-       struct adb_request req;
-       unsigned long save_l2cr;
-       unsigned long save_l3cr;
-       unsigned int pic_prio;
-       unsigned long flags;
-
-       preempt_disable();
-
-#ifdef DEBUG_FREQ
-       printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
-#endif
-       pmu_suspend();
-
-       /* Disable all interrupt sources on openpic */
-       pic_prio = mpic_cpu_get_priority();
-       mpic_cpu_set_priority(0xf);
-
-       /* Make sure the decrementer won't interrupt us */
-       asm volatile("mtdec %0" : : "r" (0x7fffffff));
-       /* Make sure any pending DEC interrupt occuring while we did
-        * the above didn't re-enable the DEC */
-       mb();
-       asm volatile("mtdec %0" : : "r" (0x7fffffff));
-
-       /* We can now disable MSR_EE */
-       local_irq_save(flags);
-
-       /* Giveup the FPU & vec */
-       enable_kernel_fp();
-
-#ifdef CONFIG_ALTIVEC
-       if (cpu_has_feature(CPU_FTR_ALTIVEC))
-               enable_kernel_altivec();
-#endif /* CONFIG_ALTIVEC */
-
-       /* Save & disable L2 and L3 caches */
-       save_l3cr = _get_L3CR();        /* (returns -1 if not available) */
-       save_l2cr = _get_L2CR();        /* (returns -1 if not available) */
-
-       /* Send the new speed command. My assumption is that this command
-        * will cause PLL_CFG[0..3] to be changed next time CPU goes to sleep
-        */
-       pmu_request(&req, NULL, 6, PMU_CPU_SPEED, 'W', 'O', 'O', 'F', low_speed);
-       while (!req.complete)
-               pmu_poll();
-
-       /* Prepare the northbridge for the speed transition */
-       pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,1);
-
-       /* Call low level code to backup CPU state and recover from
-        * hardware reset
-        */
-       low_sleep_handler();
-
-       /* Restore the northbridge */
-       pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,0);
-
-       /* Restore L2 cache */
-       if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0)
-               _set_L2CR(save_l2cr);
-       /* Restore L3 cache */
-       if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0)
-               _set_L3CR(save_l3cr);
-
-       /* Restore userland MMU context */
-       set_context(current->active_mm->context, current->active_mm->pgd);
-
-#ifdef DEBUG_FREQ
-       printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
-#endif
-
-       /* Restore low level PMU operations */
-       pmu_unlock();
-
-       /* Restore decrementer */
-       wakeup_decrementer();
-
-       /* Restore interrupts */
-       mpic_cpu_set_priority(pic_prio);
-
-       /* Let interrupts flow again ... */
-       local_irq_restore(flags);
-
-#ifdef DEBUG_FREQ
-       debug_calc_bogomips();
-#endif
-
-       pmu_resume();
-
-       preempt_enable();
-
-       return 0;
-}
-
-static int do_set_cpu_speed(int speed_mode, int notify)
-{
-       struct cpufreq_freqs freqs;
-       unsigned long l3cr;
-       static unsigned long prev_l3cr;
-
-       freqs.old = cur_freq;
-       freqs.new = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
-       freqs.cpu = smp_processor_id();
-
-       if (freqs.old == freqs.new)
-               return 0;
-
-       if (notify)
-               cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-       if (speed_mode == CPUFREQ_LOW &&
-           cpu_has_feature(CPU_FTR_L3CR)) {
-               l3cr = _get_L3CR();
-               if (l3cr & L3CR_L3E) {
-                       prev_l3cr = l3cr;
-                       _set_L3CR(0);
-               }
-       }
-       set_speed_proc(speed_mode == CPUFREQ_LOW);
-       if (speed_mode == CPUFREQ_HIGH &&
-           cpu_has_feature(CPU_FTR_L3CR)) {
-               l3cr = _get_L3CR();
-               if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr)
-                       _set_L3CR(prev_l3cr);
-       }
-       if (notify)
-               cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-       cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
-
-       return 0;
-}
-
-static unsigned int pmac_cpufreq_get_speed(unsigned int cpu)
-{
-       return cur_freq;
-}
-
-static int pmac_cpufreq_verify(struct cpufreq_policy *policy)
-{
-       return cpufreq_frequency_table_verify(policy, pmac_cpu_freqs);
-}
-
-static int pmac_cpufreq_target(        struct cpufreq_policy *policy,
-                                       unsigned int target_freq,
-                                       unsigned int relation)
-{
-       unsigned int    newstate = 0;
-
-       if (cpufreq_frequency_table_target(policy, pmac_cpu_freqs,
-                       target_freq, relation, &newstate))
-               return -EINVAL;
-
-       return do_set_cpu_speed(newstate, 1);
-}
-
-unsigned int pmac_get_one_cpufreq(int i)
-{
-       /* Supports only one CPU for now */
-       return (i == 0) ? cur_freq : 0;
-}
-
-static int pmac_cpufreq_cpu_init(struct cpufreq_policy *policy)
-{
-       if (policy->cpu != 0)
-               return -ENODEV;
-
-       policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
-       policy->cpuinfo.transition_latency      = CPUFREQ_ETERNAL;
-       policy->cur = cur_freq;
-
-       cpufreq_frequency_table_get_attr(pmac_cpu_freqs, policy->cpu);
-       return cpufreq_frequency_table_cpuinfo(policy, pmac_cpu_freqs);
-}
-
-static u32 read_gpio(struct device_node *np)
-{
-       u32 *reg = (u32 *)get_property(np, "reg", NULL);
-       u32 offset;
-
-       if (reg == NULL)
-               return 0;
-       /* That works for all keylargos but shall be fixed properly
-        * some day... The problem is that it seems we can't rely
-        * on the "reg" property of the GPIO nodes, they are either
-        * relative to the base of KeyLargo or to the base of the
-        * GPIO space, and the device-tree doesn't help.
-        */
-       offset = *reg;
-       if (offset < KEYLARGO_GPIO_LEVELS0)
-               offset += KEYLARGO_GPIO_LEVELS0;
-       return offset;
-}
-
-static int pmac_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg)
-{
-       /* Ok, this could be made a bit smarter, but let's be robust for now. We
-        * always force a speed change to high speed before sleep, to make sure
-        * we have appropriate voltage and/or bus speed for the wakeup process,
-        * and to make sure our loops_per_jiffies are "good enough", that is will
-        * not cause too short delays if we sleep in low speed and wake in high
-        * speed..
-        */
-       no_schedule = 1;
-       sleep_freq = cur_freq;
-       if (cur_freq == low_freq && !is_pmu_based)
-               do_set_cpu_speed(CPUFREQ_HIGH, 0);
-       return 0;
-}
-
-static int pmac_cpufreq_resume(struct cpufreq_policy *policy)
-{
-       /* If we resume, first check if we have a get() function */
-       if (get_speed_proc)
-               cur_freq = get_speed_proc();
-       else
-               cur_freq = 0;
-
-       /* We don't, hrm... we don't really know our speed here, best
-        * is that we force a switch to whatever it was, which is
-        * probably high speed due to our suspend() routine
-        */
-       do_set_cpu_speed(sleep_freq == low_freq ?
-                        CPUFREQ_LOW : CPUFREQ_HIGH, 0);
-
-       no_schedule = 0;
-       return 0;
-}
-
-static struct cpufreq_driver pmac_cpufreq_driver = {
-       .verify         = pmac_cpufreq_verify,
-       .target         = pmac_cpufreq_target,
-       .get            = pmac_cpufreq_get_speed,
-       .init           = pmac_cpufreq_cpu_init,
-       .suspend        = pmac_cpufreq_suspend,
-       .resume         = pmac_cpufreq_resume,
-       .flags          = CPUFREQ_PM_NO_WARN,
-       .attr           = pmac_cpu_freqs_attr,
-       .name           = "powermac",
-       .owner          = THIS_MODULE,
-};
-
-
-static int pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
-{
-       struct device_node *volt_gpio_np = of_find_node_by_name(NULL,
-                                                               "voltage-gpio");
-       struct device_node *freq_gpio_np = of_find_node_by_name(NULL,
-                                                               "frequency-gpio");
-       struct device_node *slew_done_gpio_np = of_find_node_by_name(NULL,
-                                                                    "slewing-done");
-       u32 *value;
-
-       /*
-        * Check to see if it's GPIO driven or PMU only
-        *
-        * The way we extract the GPIO address is slightly hackish, but it
-        * works well enough for now. We need to abstract the whole GPIO
-        * stuff sooner or later anyway
-        */
-
-       if (volt_gpio_np)
-               voltage_gpio = read_gpio(volt_gpio_np);
-       if (freq_gpio_np)
-               frequency_gpio = read_gpio(freq_gpio_np);
-       if (slew_done_gpio_np)
-               slew_done_gpio = read_gpio(slew_done_gpio_np);
-
-       /* If we use the frequency GPIOs, calculate the min/max speeds based
-        * on the bus frequencies
-        */
-       if (frequency_gpio && slew_done_gpio) {
-               int lenp, rc;
-               u32 *freqs, *ratio;
-
-               freqs = (u32 *)get_property(cpunode, "bus-frequencies", &lenp);
-               lenp /= sizeof(u32);
-               if (freqs == NULL || lenp != 2) {
-                       printk(KERN_ERR "cpufreq: bus-frequencies incorrect or missing\n");
-                       return 1;
-               }
-               ratio = (u32 *)get_property(cpunode, "processor-to-bus-ratio*2", NULL);
-               if (ratio == NULL) {
-                       printk(KERN_ERR "cpufreq: processor-to-bus-ratio*2 missing\n");
-                       return 1;
-               }
-
-               /* Get the min/max bus frequencies */
-               low_freq = min(freqs[0], freqs[1]);
-               hi_freq = max(freqs[0], freqs[1]);
-
-               /* Grrrr.. It _seems_ that the device-tree is lying on the low bus
-                * frequency, it claims it to be around 84Mhz on some models while
-                * it appears to be approx. 101Mhz on all. Let's hack around here...
-                * fortunately, we don't need to be too precise
-                */
-               if (low_freq < 98000000)
-                       low_freq = 101000000;
-                       
-               /* Convert those to CPU core clocks */
-               low_freq = (low_freq * (*ratio)) / 2000;
-               hi_freq = (hi_freq * (*ratio)) / 2000;
-
-               /* Now we get the frequencies, we read the GPIO to see what is out current
-                * speed
-                */
-               rc = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
-               cur_freq = (rc & 0x01) ? hi_freq : low_freq;
-
-               set_speed_proc = gpios_set_cpu_speed;
-               return 1;
-       }
-
-       /* If we use the PMU, look for the min & max frequencies in the
-        * device-tree
-        */
-       value = (u32 *)get_property(cpunode, "min-clock-frequency", NULL);
-       if (!value)
-               return 1;
-       low_freq = (*value) / 1000;
-       /* The PowerBook G4 12" (PowerBook6,1) has an error in the device-tree
-        * here */
-       if (low_freq < 100000)
-               low_freq *= 10;
-
-       value = (u32 *)get_property(cpunode, "max-clock-frequency", NULL);
-       if (!value)
-               return 1;
-       hi_freq = (*value) / 1000;
-       set_speed_proc = pmu_set_cpu_speed;
-       is_pmu_based = 1;
-
-       return 0;
-}
-
-static int pmac_cpufreq_init_7447A(struct device_node *cpunode)
-{
-       struct device_node *volt_gpio_np;
-
-       if (get_property(cpunode, "dynamic-power-step", NULL) == NULL)
-               return 1;
-
-       volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
-       if (volt_gpio_np)
-               voltage_gpio = read_gpio(volt_gpio_np);
-       if (!voltage_gpio){
-               printk(KERN_ERR "cpufreq: missing cpu-vcore-select gpio\n");
-               return 1;
-       }
-
-       /* OF only reports the high frequency */
-       hi_freq = cur_freq;
-       low_freq = cur_freq/2;
-
-       /* Read actual frequency from CPU */
-       cur_freq = dfs_get_cpu_speed();
-       set_speed_proc = dfs_set_cpu_speed;
-       get_speed_proc = dfs_get_cpu_speed;
-
-       return 0;
-}
-
-static int pmac_cpufreq_init_750FX(struct device_node *cpunode)
-{
-       struct device_node *volt_gpio_np;
-       u32 pvr, *value;
-
-       if (get_property(cpunode, "dynamic-power-step", NULL) == NULL)
-               return 1;
-
-       hi_freq = cur_freq;
-       value = (u32 *)get_property(cpunode, "reduced-clock-frequency", NULL);
-       if (!value)
-               return 1;
-       low_freq = (*value) / 1000;
-
-       volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
-       if (volt_gpio_np)
-               voltage_gpio = read_gpio(volt_gpio_np);
-
-       pvr = mfspr(SPRN_PVR);
-       has_cpu_l2lve = !((pvr & 0xf00) == 0x100);
-
-       set_speed_proc = cpu_750fx_cpu_speed;
-       get_speed_proc = cpu_750fx_get_cpu_speed;
-       cur_freq = cpu_750fx_get_cpu_speed();
-
-       return 0;
-}
-
-/* Currently, we support the following machines:
- *
- *  - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
- *  - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
- *  - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
- *  - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz)
- *  - iBook2 500/600 (PMU based, 400Mhz & 500/600Mhz)
- *  - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage)
- *  - Recent MacRISC3 laptops
- *  - All new machines with 7447A CPUs
- */
-static int __init pmac_cpufreq_setup(void)
-{
-       struct device_node      *cpunode;
-       u32                     *value;
-
-       if (strstr(cmd_line, "nocpufreq"))
-               return 0;
-
-       /* Assume only one CPU */
-       cpunode = find_type_devices("cpu");
-       if (!cpunode)
-               goto out;
-
-       /* Get current cpu clock freq */
-       value = (u32 *)get_property(cpunode, "clock-frequency", NULL);
-       if (!value)
-               goto out;
-       cur_freq = (*value) / 1000;
-
-       /*  Check for 7447A based MacRISC3 */
-       if (machine_is_compatible("MacRISC3") &&
-           get_property(cpunode, "dynamic-power-step", NULL) &&
-           PVR_VER(mfspr(SPRN_PVR)) == 0x8003) {
-               pmac_cpufreq_init_7447A(cpunode);
-       /* Check for other MacRISC3 machines */
-       } else if (machine_is_compatible("PowerBook3,4") ||
-                  machine_is_compatible("PowerBook3,5") ||
-                  machine_is_compatible("MacRISC3")) {
-               pmac_cpufreq_init_MacRISC3(cpunode);
-       /* Else check for iBook2 500/600 */
-       } else if (machine_is_compatible("PowerBook4,1")) {
-               hi_freq = cur_freq;
-               low_freq = 400000;
-               set_speed_proc = pmu_set_cpu_speed;
-               is_pmu_based = 1;
-       }
-       /* Else check for TiPb 550 */
-       else if (machine_is_compatible("PowerBook3,3") && cur_freq == 550000) {
-               hi_freq = cur_freq;
-               low_freq = 500000;
-               set_speed_proc = pmu_set_cpu_speed;
-               is_pmu_based = 1;
-       }
-       /* Else check for TiPb 400 & 500 */
-       else if (machine_is_compatible("PowerBook3,2")) {
-               /* We only know about the 400 MHz and the 500Mhz model
-                * they both have 300 MHz as low frequency
-                */
-               if (cur_freq < 350000 || cur_freq > 550000)
-                       goto out;
-               hi_freq = cur_freq;
-               low_freq = 300000;
-               set_speed_proc = pmu_set_cpu_speed;
-               is_pmu_based = 1;
-       }
-       /* Else check for 750FX */
-       else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000)
-               pmac_cpufreq_init_750FX(cpunode);
-out:
-       if (set_speed_proc == NULL)
-               return -ENODEV;
-
-       pmac_cpu_freqs[CPUFREQ_LOW].frequency = low_freq;
-       pmac_cpu_freqs[CPUFREQ_HIGH].frequency = hi_freq;
-
-       printk(KERN_INFO "Registering PowerMac CPU frequency driver\n");
-       printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Boot: %d Mhz\n",
-              low_freq/1000, hi_freq/1000, cur_freq/1000);
-
-       return cpufreq_register_driver(&pmac_cpufreq_driver);
-}
-
-module_init(pmac_cpufreq_setup);
-
diff --git a/arch/powerpc/platforms/powermac/cpufreq_32.c b/arch/powerpc/platforms/powermac/cpufreq_32.c
new file mode 100644 (file)
index 0000000..7960a7b
--- /dev/null
@@ -0,0 +1,727 @@
+/*
+ *  arch/ppc/platforms/pmac_cpufreq.c
+ *
+ *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ *  Copyright (C) 2004        John Steele Scott <toojays@toojays.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * TODO: Need a big cleanup here. Basically, we need to have different
+ * cpufreq_driver structures for the different type of HW instead of the
+ * current mess. We also need to better deal with the detection of the
+ * type of machine.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/adb.h>
+#include <linux/pmu.h>
+#include <linux/slab.h>
+#include <linux/cpufreq.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+#include <linux/i2c.h>
+#include <linux/hardirq.h>
+#include <asm/prom.h>
+#include <asm/machdep.h>
+#include <asm/irq.h>
+#include <asm/pmac_feature.h>
+#include <asm/mmu_context.h>
+#include <asm/sections.h>
+#include <asm/cputable.h>
+#include <asm/time.h>
+#include <asm/system.h>
+#include <asm/mpic.h>
+#include <asm/keylargo.h>
+
+/* WARNING !!! This will cause calibrate_delay() to be called,
+ * but this is an __init function ! So you MUST go edit
+ * init/main.c to make it non-init before enabling DEBUG_FREQ
+ */
+#undef DEBUG_FREQ
+
+/*
+ * There is a problem with the core cpufreq code on SMP kernels,
+ * it won't recalculate the Bogomips properly
+ */
+#ifdef CONFIG_SMP
+#warning "WARNING, CPUFREQ not recommended on SMP kernels"
+#endif
+
+extern void low_choose_7447a_dfs(int dfs);
+extern void low_choose_750fx_pll(int pll);
+extern void low_sleep_handler(void);
+
+/*
+ * Currently, PowerMac cpufreq supports only high & low frequencies
+ * that are set by the firmware
+ */
+static unsigned int low_freq;
+static unsigned int hi_freq;
+static unsigned int cur_freq;
+static unsigned int sleep_freq;
+
+/*
+ * Different models uses different mecanisms to switch the frequency
+ */
+static int (*set_speed_proc)(int low_speed);
+static unsigned int (*get_speed_proc)(void);
+
+/*
+ * Some definitions used by the various speedprocs
+ */
+static u32 voltage_gpio;
+static u32 frequency_gpio;
+static u32 slew_done_gpio;
+static int no_schedule;
+static int has_cpu_l2lve;
+static int is_pmu_based;
+
+/* There are only two frequency states for each processor. Values
+ * are in kHz for the time being.
+ */
+#define CPUFREQ_HIGH                  0
+#define CPUFREQ_LOW                   1
+
+static struct cpufreq_frequency_table pmac_cpu_freqs[] = {
+       {CPUFREQ_HIGH,          0},
+       {CPUFREQ_LOW,           0},
+       {0,                     CPUFREQ_TABLE_END},
+};
+
+static struct freq_attr* pmac_cpu_freqs_attr[] = {
+       &cpufreq_freq_attr_scaling_available_freqs,
+       NULL,
+};
+
+static inline void local_delay(unsigned long ms)
+{
+       if (no_schedule)
+               mdelay(ms);
+       else
+               msleep(ms);
+}
+
+#ifdef DEBUG_FREQ
+static inline void debug_calc_bogomips(void)
+{
+       /* This will cause a recalc of bogomips and display the
+        * result. We backup/restore the value to avoid affecting the
+        * core cpufreq framework's own calculation.
+        */
+       extern void calibrate_delay(void);
+
+       unsigned long save_lpj = loops_per_jiffy;
+       calibrate_delay();
+       loops_per_jiffy = save_lpj;
+}
+#endif /* DEBUG_FREQ */
+
+/* Switch CPU speed under 750FX CPU control
+ */
+static int cpu_750fx_cpu_speed(int low_speed)
+{
+       u32 hid2;
+
+       if (low_speed == 0) {
+               /* ramping up, set voltage first */
+               pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
+               /* Make sure we sleep for at least 1ms */
+               local_delay(10);
+
+               /* tweak L2 for high voltage */
+               if (has_cpu_l2lve) {
+                       hid2 = mfspr(SPRN_HID2);
+                       hid2 &= ~0x2000;
+                       mtspr(SPRN_HID2, hid2);
+               }
+       }
+#ifdef CONFIG_6xx
+       low_choose_750fx_pll(low_speed);
+#endif
+       if (low_speed == 1) {
+               /* tweak L2 for low voltage */
+               if (has_cpu_l2lve) {
+                       hid2 = mfspr(SPRN_HID2);
+                       hid2 |= 0x2000;
+                       mtspr(SPRN_HID2, hid2);
+               }
+
+               /* ramping down, set voltage last */
+               pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
+               local_delay(10);
+       }
+
+       return 0;
+}
+
+static unsigned int cpu_750fx_get_cpu_speed(void)
+{
+       if (mfspr(SPRN_HID1) & HID1_PS)
+               return low_freq;
+       else
+               return hi_freq;
+}
+
+/* Switch CPU speed using DFS */
+static int dfs_set_cpu_speed(int low_speed)
+{
+       if (low_speed == 0) {
+               /* ramping up, set voltage first */
+               pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
+               /* Make sure we sleep for at least 1ms */
+               local_delay(1);
+       }
+
+       /* set frequency */
+#ifdef CONFIG_6xx
+       low_choose_7447a_dfs(low_speed);
+#endif
+       udelay(100);
+
+       if (low_speed == 1) {
+               /* ramping down, set voltage last */
+               pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
+               local_delay(1);
+       }
+
+       return 0;
+}
+
+static unsigned int dfs_get_cpu_speed(void)
+{
+       if (mfspr(SPRN_HID1) & HID1_DFS)
+               return low_freq;
+       else
+               return hi_freq;
+}
+
+
+/* Switch CPU speed using slewing GPIOs
+ */
+static int gpios_set_cpu_speed(int low_speed)
+{
+       int gpio, timeout = 0;
+
+       /* If ramping up, set voltage first */
+       if (low_speed == 0) {
+               pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
+               /* Delay is way too big but it's ok, we schedule */
+               local_delay(10);
+       }
+
+       /* Set frequency */
+       gpio =  pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
+       if (low_speed == ((gpio & 0x01) == 0))
+               goto skip;
+
+       pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, frequency_gpio,
+                         low_speed ? 0x04 : 0x05);
+       udelay(200);
+       do {
+               if (++timeout > 100)
+                       break;
+               local_delay(1);
+               gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, slew_done_gpio, 0);
+       } while((gpio & 0x02) == 0);
+ skip:
+       /* If ramping down, set voltage last */
+       if (low_speed == 1) {
+               pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
+               /* Delay is way too big but it's ok, we schedule */
+               local_delay(10);
+       }
+
+#ifdef DEBUG_FREQ
+       debug_calc_bogomips();
+#endif
+
+       return 0;
+}
+
+/* Switch CPU speed under PMU control
+ */
+static int pmu_set_cpu_speed(int low_speed)
+{
+       struct adb_request req;
+       unsigned long save_l2cr;
+       unsigned long save_l3cr;
+       unsigned int pic_prio;
+       unsigned long flags;
+
+       preempt_disable();
+
+#ifdef DEBUG_FREQ
+       printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
+#endif
+       pmu_suspend();
+
+       /* Disable all interrupt sources on openpic */
+       pic_prio = mpic_cpu_get_priority();
+       mpic_cpu_set_priority(0xf);
+
+       /* Make sure the decrementer won't interrupt us */
+       asm volatile("mtdec %0" : : "r" (0x7fffffff));
+       /* Make sure any pending DEC interrupt occuring while we did
+        * the above didn't re-enable the DEC */
+       mb();
+       asm volatile("mtdec %0" : : "r" (0x7fffffff));
+
+       /* We can now disable MSR_EE */
+       local_irq_save(flags);
+
+       /* Giveup the FPU & vec */
+       enable_kernel_fp();
+
+#ifdef CONFIG_ALTIVEC
+       if (cpu_has_feature(CPU_FTR_ALTIVEC))
+               enable_kernel_altivec();
+#endif /* CONFIG_ALTIVEC */
+
+       /* Save & disable L2 and L3 caches */
+       save_l3cr = _get_L3CR();        /* (returns -1 if not available) */
+       save_l2cr = _get_L2CR();        /* (returns -1 if not available) */
+
+       /* Send the new speed command. My assumption is that this command
+        * will cause PLL_CFG[0..3] to be changed next time CPU goes to sleep
+        */
+       pmu_request(&req, NULL, 6, PMU_CPU_SPEED, 'W', 'O', 'O', 'F', low_speed);
+       while (!req.complete)
+               pmu_poll();
+
+       /* Prepare the northbridge for the speed transition */
+       pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,1);
+
+       /* Call low level code to backup CPU state and recover from
+        * hardware reset
+        */
+       low_sleep_handler();
+
+       /* Restore the northbridge */
+       pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,0);
+
+       /* Restore L2 cache */
+       if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0)
+               _set_L2CR(save_l2cr);
+       /* Restore L3 cache */
+       if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0)
+               _set_L3CR(save_l3cr);
+
+       /* Restore userland MMU context */
+       set_context(current->active_mm->context, current->active_mm->pgd);
+
+#ifdef DEBUG_FREQ
+       printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
+#endif
+
+       /* Restore low level PMU operations */
+       pmu_unlock();
+
+       /* Restore decrementer */
+       wakeup_decrementer();
+
+       /* Restore interrupts */
+       mpic_cpu_set_priority(pic_prio);
+
+       /* Let interrupts flow again ... */
+       local_irq_restore(flags);
+
+#ifdef DEBUG_FREQ
+       debug_calc_bogomips();
+#endif
+
+       pmu_resume();
+
+       preempt_enable();
+
+       return 0;
+}
+
+static int do_set_cpu_speed(int speed_mode, int notify)
+{
+       struct cpufreq_freqs freqs;
+       unsigned long l3cr;
+       static unsigned long prev_l3cr;
+
+       freqs.old = cur_freq;
+       freqs.new = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
+       freqs.cpu = smp_processor_id();
+
+       if (freqs.old == freqs.new)
+               return 0;
+
+       if (notify)
+               cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+       if (speed_mode == CPUFREQ_LOW &&
+           cpu_has_feature(CPU_FTR_L3CR)) {
+               l3cr = _get_L3CR();
+               if (l3cr & L3CR_L3E) {
+                       prev_l3cr = l3cr;
+                       _set_L3CR(0);
+               }
+       }
+       set_speed_proc(speed_mode == CPUFREQ_LOW);
+       if (speed_mode == CPUFREQ_HIGH &&
+           cpu_has_feature(CPU_FTR_L3CR)) {
+               l3cr = _get_L3CR();
+               if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr)
+                       _set_L3CR(prev_l3cr);
+       }
+       if (notify)
+               cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+       cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
+
+       return 0;
+}
+
+static unsigned int pmac_cpufreq_get_speed(unsigned int cpu)
+{
+       return cur_freq;
+}
+
+static int pmac_cpufreq_verify(struct cpufreq_policy *policy)
+{
+       return cpufreq_frequency_table_verify(policy, pmac_cpu_freqs);
+}
+
+static int pmac_cpufreq_target(        struct cpufreq_policy *policy,
+                                       unsigned int target_freq,
+                                       unsigned int relation)
+{
+       unsigned int    newstate = 0;
+       int             rc;
+
+       if (cpufreq_frequency_table_target(policy, pmac_cpu_freqs,
+                       target_freq, relation, &newstate))
+               return -EINVAL;
+
+       rc = do_set_cpu_speed(newstate, 1);
+
+       ppc_proc_freq = cur_freq * 1000ul;
+       return rc;
+}
+
+static int pmac_cpufreq_cpu_init(struct cpufreq_policy *policy)
+{
+       if (policy->cpu != 0)
+               return -ENODEV;
+
+       policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+       policy->cpuinfo.transition_latency      = CPUFREQ_ETERNAL;
+       policy->cur = cur_freq;
+
+       cpufreq_frequency_table_get_attr(pmac_cpu_freqs, policy->cpu);
+       return cpufreq_frequency_table_cpuinfo(policy, pmac_cpu_freqs);
+}
+
+static u32 read_gpio(struct device_node *np)
+{
+       u32 *reg = (u32 *)get_property(np, "reg", NULL);
+       u32 offset;
+
+       if (reg == NULL)
+               return 0;
+       /* That works for all keylargos but shall be fixed properly
+        * some day... The problem is that it seems we can't rely
+        * on the "reg" property of the GPIO nodes, they are either
+        * relative to the base of KeyLargo or to the base of the
+        * GPIO space, and the device-tree doesn't help.
+        */
+       offset = *reg;
+       if (offset < KEYLARGO_GPIO_LEVELS0)
+               offset += KEYLARGO_GPIO_LEVELS0;
+       return offset;
+}
+
+static int pmac_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg)
+{
+       /* Ok, this could be made a bit smarter, but let's be robust for now. We
+        * always force a speed change to high speed before sleep, to make sure
+        * we have appropriate voltage and/or bus speed for the wakeup process,
+        * and to make sure our loops_per_jiffies are "good enough", that is will
+        * not cause too short delays if we sleep in low speed and wake in high
+        * speed..
+        */
+       no_schedule = 1;
+       sleep_freq = cur_freq;
+       if (cur_freq == low_freq && !is_pmu_based)
+               do_set_cpu_speed(CPUFREQ_HIGH, 0);
+       return 0;
+}
+
+static int pmac_cpufreq_resume(struct cpufreq_policy *policy)
+{
+       /* If we resume, first check if we have a get() function */
+       if (get_speed_proc)
+               cur_freq = get_speed_proc();
+       else)
+               cur_freq = 0;
+
+       /* We don't, hrm... we don't really know our speed here, best
+        * is that we force a switch to whatever it was, which is
+        * probably high speed due to our suspend() routine
+        */
+       do_set_cpu_speed(sleep_freq == low_freq ?
+                        CPUFREQ_LOW : CPUFREQ_HIGH, 0);
+
+       ppc_proc_freq = cur_freq * 1000ul;
+
+       no_schedule = 0;
+       return 0;
+}
+
+static struct cpufreq_driver pmac_cpufreq_driver = {
+       .verify         = pmac_cpufreq_verify,
+       .target         = pmac_cpufreq_target,
+       .get            = pmac_cpufreq_get_speed,
+       .init           = pmac_cpufreq_cpu_init,
+       .suspend        = pmac_cpufreq_suspend,
+       .resume         = pmac_cpufreq_resume,
+       .flags          = CPUFREQ_PM_NO_WARN,
+       .attr           = pmac_cpu_freqs_attr,
+       .name           = "powermac",
+       .owner          = THIS_MODULE,
+};
+
+
+static int pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
+{
+       struct device_node *volt_gpio_np = of_find_node_by_name(NULL,
+                                                               "voltage-gpio");
+       struct device_node *freq_gpio_np = of_find_node_by_name(NULL,
+                                                               "frequency-gpio");
+       struct device_node *slew_done_gpio_np = of_find_node_by_name(NULL,
+                                                                    "slewing-done");
+       u32 *value;
+
+       /*
+        * Check to see if it's GPIO driven or PMU only
+        *
+        * The way we extract the GPIO address is slightly hackish, but it
+        * works well enough for now. We need to abstract the whole GPIO
+        * stuff sooner or later anyway
+        */
+
+       if (volt_gpio_np)
+               voltage_gpio = read_gpio(volt_gpio_np);
+       if (freq_gpio_np)
+               frequency_gpio = read_gpio(freq_gpio_np);
+       if (slew_done_gpio_np)
+               slew_done_gpio = read_gpio(slew_done_gpio_np);
+
+       /* If we use the frequency GPIOs, calculate the min/max speeds based
+        * on the bus frequencies
+        */
+       if (frequency_gpio && slew_done_gpio) {
+               int lenp, rc;
+               u32 *freqs, *ratio;
+
+               freqs = (u32 *)get_property(cpunode, "bus-frequencies", &lenp);
+               lenp /= sizeof(u32);
+               if (freqs == NULL || lenp != 2) {
+                       printk(KERN_ERR "cpufreq: bus-frequencies incorrect or missing\n");
+                       return 1;
+               }
+               ratio = (u32 *)get_property(cpunode, "processor-to-bus-ratio*2", NULL);
+               if (ratio == NULL) {
+                       printk(KERN_ERR "cpufreq: processor-to-bus-ratio*2 missing\n");
+                       return 1;
+               }
+
+               /* Get the min/max bus frequencies */
+               low_freq = min(freqs[0], freqs[1]);
+               hi_freq = max(freqs[0], freqs[1]);
+
+               /* Grrrr.. It _seems_ that the device-tree is lying on the low bus
+                * frequency, it claims it to be around 84Mhz on some models while
+                * it appears to be approx. 101Mhz on all. Let's hack around here...
+                * fortunately, we don't need to be too precise
+                */
+               if (low_freq < 98000000)
+                       low_freq = 101000000;
+
+               /* Convert those to CPU core clocks */
+               low_freq = (low_freq * (*ratio)) / 2000;
+               hi_freq = (hi_freq * (*ratio)) / 2000;
+
+               /* Now we get the frequencies, we read the GPIO to see what is out current
+                * speed
+                */
+               rc = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
+               cur_freq = (rc & 0x01) ? hi_freq : low_freq;
+
+               set_speed_proc = gpios_set_cpu_speed;
+               return 1;
+       }
+
+       /* If we use the PMU, look for the min & max frequencies in the
+        * device-tree
+        */
+       value = (u32 *)get_property(cpunode, "min-clock-frequency", NULL);
+       if (!value)
+               return 1;
+       low_freq = (*value) / 1000;
+       /* The PowerBook G4 12" (PowerBook6,1) has an error in the device-tree
+        * here */
+       if (low_freq < 100000)
+               low_freq *= 10;
+
+       value = (u32 *)get_property(cpunode, "max-clock-frequency", NULL);
+       if (!value)
+               return 1;
+       hi_freq = (*value) / 1000;
+       set_speed_proc = pmu_set_cpu_speed;
+       is_pmu_based = 1;
+
+       return 0;
+}
+
+static int pmac_cpufreq_init_7447A(struct device_node *cpunode)
+{
+       struct device_node *volt_gpio_np;
+
+       if (get_property(cpunode, "dynamic-power-step", NULL) == NULL)
+               return 1;
+
+       volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
+       if (volt_gpio_np)
+               voltage_gpio = read_gpio(volt_gpio_np);
+       if (!voltage_gpio){
+               printk(KERN_ERR "cpufreq: missing cpu-vcore-select gpio\n");
+               return 1;
+       }
+
+       /* OF only reports the high frequency */
+       hi_freq = cur_freq;
+       low_freq = cur_freq/2;
+
+       /* Read actual frequency from CPU */
+       cur_freq = dfs_get_cpu_speed();
+       set_speed_proc = dfs_set_cpu_speed;
+       get_speed_proc = dfs_get_cpu_speed;
+
+       return 0;
+}
+
+static int pmac_cpufreq_init_750FX(struct device_node *cpunode)
+{
+       struct device_node *volt_gpio_np;
+       u32 pvr, *value;
+
+       if (get_property(cpunode, "dynamic-power-step", NULL) == NULL)
+               return 1;
+
+       hi_freq = cur_freq;
+       value = (u32 *)get_property(cpunode, "reduced-clock-frequency", NULL);
+       if (!value)
+               return 1;
+       low_freq = (*value) / 1000;
+
+       volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
+       if (volt_gpio_np)
+               voltage_gpio = read_gpio(volt_gpio_np);
+
+       pvr = mfspr(SPRN_PVR);
+       has_cpu_l2lve = !((pvr & 0xf00) == 0x100);
+
+       set_speed_proc = cpu_750fx_cpu_speed;
+       get_speed_proc = cpu_750fx_get_cpu_speed;
+       cur_freq = cpu_750fx_get_cpu_speed();
+
+       return 0;
+}
+
+/* Currently, we support the following machines:
+ *
+ *  - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
+ *  - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
+ *  - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
+ *  - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz)
+ *  - iBook2 500/600 (PMU based, 400Mhz & 500/600Mhz)
+ *  - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage)
+ *  - Recent MacRISC3 laptops
+ *  - All new machines with 7447A CPUs
+ */
+static int __init pmac_cpufreq_setup(void)
+{
+       struct device_node      *cpunode;
+       u32                     *value;
+
+       if (strstr(cmd_line, "nocpufreq"))
+               return 0;
+
+       /* Assume only one CPU */
+       cpunode = find_type_devices("cpu");
+       if (!cpunode)
+               goto out;
+
+       /* Get current cpu clock freq */
+       value = (u32 *)get_property(cpunode, "clock-frequency", NULL);
+       if (!value)
+               goto out;
+       cur_freq = (*value) / 1000;
+
+       /*  Check for 7447A based MacRISC3 */
+       if (machine_is_compatible("MacRISC3") &&
+           get_property(cpunode, "dynamic-power-step", NULL) &&
+           PVR_VER(mfspr(SPRN_PVR)) == 0x8003) {
+               pmac_cpufreq_init_7447A(cpunode);
+       /* Check for other MacRISC3 machines */
+       } else if (machine_is_compatible("PowerBook3,4") ||
+                  machine_is_compatible("PowerBook3,5") ||
+                  machine_is_compatible("MacRISC3")) {
+               pmac_cpufreq_init_MacRISC3(cpunode);
+       /* Else check for iBook2 500/600 */
+       } else if (machine_is_compatible("PowerBook4,1")) {
+               hi_freq = cur_freq;
+               low_freq = 400000;
+               set_speed_proc = pmu_set_cpu_speed;
+               is_pmu_based = 1;
+       }
+       /* Else check for TiPb 550 */
+       else if (machine_is_compatible("PowerBook3,3") && cur_freq == 550000) {
+               hi_freq = cur_freq;
+               low_freq = 500000;
+               set_speed_proc = pmu_set_cpu_speed;
+               is_pmu_based = 1;
+       }
+       /* Else check for TiPb 400 & 500 */
+       else if (machine_is_compatible("PowerBook3,2")) {
+               /* We only know about the 400 MHz and the 500Mhz model
+                * they both have 300 MHz as low frequency
+                */
+               if (cur_freq < 350000 || cur_freq > 550000)
+                       goto out;
+               hi_freq = cur_freq;
+               low_freq = 300000;
+               set_speed_proc = pmu_set_cpu_speed;
+               is_pmu_based = 1;
+       }
+       /* Else check for 750FX */
+       else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000)
+               pmac_cpufreq_init_750FX(cpunode);
+out:
+       if (set_speed_proc == NULL)
+               return -ENODEV;
+
+       pmac_cpu_freqs[CPUFREQ_LOW].frequency = low_freq;
+       pmac_cpu_freqs[CPUFREQ_HIGH].frequency = hi_freq;
+       ppc_proc_freq = cur_freq * 1000ul;
+
+       printk(KERN_INFO "Registering PowerMac CPU frequency driver\n");
+       printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Boot: %d Mhz\n",
+              low_freq/1000, hi_freq/1000, cur_freq/1000);
+
+       return cpufreq_register_driver(&pmac_cpufreq_driver);
+}
+
+module_init(pmac_cpufreq_setup);
+
diff --git a/arch/powerpc/platforms/powermac/cpufreq_64.c b/arch/powerpc/platforms/powermac/cpufreq_64.c
new file mode 100644 (file)
index 0000000..3915034
--- /dev/null
@@ -0,0 +1,323 @@
+/*
+ *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ *  and                       Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
+ * that is iMac G5 and latest single CPU desktop.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/cpufreq.h>
+#include <linux/init.h>
+#include <linux/completion.h>
+#include <asm/prom.h>
+#include <asm/machdep.h>
+#include <asm/irq.h>
+#include <asm/sections.h>
+#include <asm/cputable.h>
+#include <asm/time.h>
+#include <asm/smu.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt...) printk(fmt)
+#else
+#define DBG(fmt...)
+#endif
+
+/* see 970FX user manual */
+
+#define SCOM_PCR 0x0aa001                      /* PCR scom addr */
+
+#define PCR_HILO_SELECT                0x80000000U     /* 1 = PCR, 0 = PCRH */
+#define PCR_SPEED_FULL         0x00000000U     /* 1:1 speed value */
+#define PCR_SPEED_HALF         0x00020000U     /* 1:2 speed value */
+#define PCR_SPEED_QUARTER      0x00040000U     /* 1:4 speed value */
+#define PCR_SPEED_MASK         0x000e0000U     /* speed mask */
+#define PCR_SPEED_SHIFT                17
+#define PCR_FREQ_REQ_VALID     0x00010000U     /* freq request valid */
+#define PCR_VOLT_REQ_VALID     0x00008000U     /* volt request valid */
+#define PCR_TARGET_TIME_MASK   0x00006000U     /* target time */
+#define PCR_STATLAT_MASK       0x00001f00U     /* STATLAT value */
+#define PCR_SNOOPLAT_MASK      0x000000f0U     /* SNOOPLAT value */
+#define PCR_SNOOPACC_MASK      0x0000000fU     /* SNOOPACC value */
+
+#define SCOM_PSR 0x408001                      /* PSR scom addr */
+/* warning: PSR is a 64 bits register */
+#define PSR_CMD_RECEIVED       0x2000000000000000U   /* command received */
+#define PSR_CMD_COMPLETED      0x1000000000000000U   /* command completed */
+#define PSR_CUR_SPEED_MASK     0x0300000000000000U   /* current speed */
+#define PSR_CUR_SPEED_SHIFT    (56)
+
+/*
+ * The G5 only supports two frequencies (Quarter speed is not supported)
+ */
+#define CPUFREQ_HIGH                  0
+#define CPUFREQ_LOW                   1
+
+static struct cpufreq_frequency_table g5_cpu_freqs[] = {
+       {CPUFREQ_HIGH,          0},
+       {CPUFREQ_LOW,           0},
+       {0,                     CPUFREQ_TABLE_END},
+};
+
+static struct freq_attr* g5_cpu_freqs_attr[] = {
+       &cpufreq_freq_attr_scaling_available_freqs,
+       NULL,
+};
+
+/* Power mode data is an array of the 32 bits PCR values to use for
+ * the various frequencies, retreived from the device-tree
+ */
+static u32 *g5_pmode_data;
+static int g5_pmode_max;
+static int g5_pmode_cur;
+
+static DECLARE_MUTEX(g5_switch_mutex);
+
+
+static struct smu_sdbp_fvt *g5_fvt_table;      /* table of op. points */
+static int g5_fvt_count;                       /* number of op. points */
+static int g5_fvt_cur;                         /* current op. point */
+
+/* ----------------- real hardware interface */
+
+static void g5_switch_volt(int speed_mode)
+{
+       struct smu_simple_cmd   cmd;
+
+       DECLARE_COMPLETION(comp);
+       smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
+                        &comp, 'V', 'S', 'L', 'E', 'W',
+                        0xff, g5_fvt_cur+1, speed_mode);
+       wait_for_completion(&comp);
+}
+
+static int g5_switch_freq(int speed_mode)
+{
+       struct cpufreq_freqs freqs;
+       int to;
+
+       if (g5_pmode_cur == speed_mode)
+               return 0;
+
+       down(&g5_switch_mutex);
+
+       freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency;
+       freqs.new = g5_cpu_freqs[speed_mode].frequency;
+       freqs.cpu = 0;
+
+       cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+       /* If frequency is going up, first ramp up the voltage */
+       if (speed_mode < g5_pmode_cur)
+               g5_switch_volt(speed_mode);
+
+       /* Clear PCR high */
+       scom970_write(SCOM_PCR, 0);
+       /* Clear PCR low */
+               scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
+       /* Set PCR low */
+       scom970_write(SCOM_PCR, PCR_HILO_SELECT |
+                     g5_pmode_data[speed_mode]);
+
+       /* Wait for completion */
+       for (to = 0; to < 10; to++) {
+               unsigned long psr = scom970_read(SCOM_PSR);
+
+               if ((psr & PSR_CMD_RECEIVED) == 0 &&
+                   (((psr >> PSR_CUR_SPEED_SHIFT) ^
+                     (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
+                   == 0)
+                       break;
+               if (psr & PSR_CMD_COMPLETED)
+                       break;
+               udelay(100);
+       }
+
+       /* If frequency is going down, last ramp the voltage */
+       if (speed_mode > g5_pmode_cur)
+               g5_switch_volt(speed_mode);
+
+       g5_pmode_cur = speed_mode;
+       ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
+
+       cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+       up(&g5_switch_mutex);
+
+       return 0;
+}
+
+static int g5_query_freq(void)
+{
+       unsigned long psr = scom970_read(SCOM_PSR);
+       int i;
+
+       for (i = 0; i <= g5_pmode_max; i++)
+               if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
+                     (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
+                       break;
+       return i;
+}
+
+/* ----------------- cpufreq bookkeeping */
+
+static int g5_cpufreq_verify(struct cpufreq_policy *policy)
+{
+       return cpufreq_frequency_table_verify(policy, g5_cpu_freqs);
+}
+
+static int g5_cpufreq_target(struct cpufreq_policy *policy,
+       unsigned int target_freq, unsigned int relation)
+{
+       unsigned int    newstate = 0;
+
+       if (cpufreq_frequency_table_target(policy, g5_cpu_freqs,
+                       target_freq, relation, &newstate))
+               return -EINVAL;
+
+       return g5_switch_freq(newstate);
+}
+
+static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
+{
+       return g5_cpu_freqs[g5_pmode_cur].frequency;
+}
+
+static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
+{
+       if (policy->cpu != 0)
+               return -ENODEV;
+
+       policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+       policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+       policy->cur = g5_cpu_freqs[g5_query_freq()].frequency;
+       cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu);
+
+       return cpufreq_frequency_table_cpuinfo(policy,
+               g5_cpu_freqs);
+}
+
+
+static struct cpufreq_driver g5_cpufreq_driver = {
+       .name           = "powermac",
+       .owner          = THIS_MODULE,
+       .flags          = CPUFREQ_CONST_LOOPS,
+       .init           = g5_cpufreq_cpu_init,
+       .verify         = g5_cpufreq_verify,
+       .target         = g5_cpufreq_target,
+       .get            = g5_cpufreq_get_speed,
+       .attr           = g5_cpu_freqs_attr,
+};
+
+
+static int __init g5_cpufreq_init(void)
+{
+       struct device_node *cpunode;
+       unsigned int psize, ssize;
+       struct smu_sdbp_header *shdr;
+       unsigned long max_freq;
+       u32 *valp;
+       int rc = -ENODEV;
+
+       /* Look for CPU and SMU nodes */
+       cpunode = of_find_node_by_type(NULL, "cpu");
+       if (!cpunode) {
+               DBG("No CPU node !\n");
+               return -ENODEV;
+       }
+
+       /* Check 970FX for now */
+       valp = (u32 *)get_property(cpunode, "cpu-version", NULL);
+       if (!valp) {
+               DBG("No cpu-version property !\n");
+               goto bail_noprops;
+       }
+       if (((*valp) >> 16) != 0x3c) {
+               DBG("Wrong CPU version: %08x\n", *valp);
+               goto bail_noprops;
+       }
+
+       /* Look for the powertune data in the device-tree */
+       g5_pmode_data = (u32 *)get_property(cpunode, "power-mode-data",&psize);
+       if (!g5_pmode_data) {
+               DBG("No power-mode-data !\n");
+               goto bail_noprops;
+       }
+       g5_pmode_max = psize / sizeof(u32) - 1;
+
+       /* Look for the FVT table */
+       shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
+       if (!shdr)
+               goto bail_noprops;
+       g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
+       ssize = (shdr->len * sizeof(u32)) - sizeof(struct smu_sdbp_header);
+       g5_fvt_count = ssize / sizeof(struct smu_sdbp_fvt);
+       g5_fvt_cur = 0;
+
+       /* Sanity checking */
+       if (g5_fvt_count < 1 || g5_pmode_max < 1)
+               goto bail_noprops;
+
+       /*
+        * From what I see, clock-frequency is always the maximal frequency.
+        * The current driver can not slew sysclk yet, so we really only deal
+        * with powertune steps for now. We also only implement full freq and
+        * half freq in this version. So far, I haven't yet seen a machine
+        * supporting anything else.
+        */
+       valp = (u32 *)get_property(cpunode, "clock-frequency", NULL);
+       if (!valp)
+               return -ENODEV;
+       max_freq = (*valp)/1000;
+       g5_cpu_freqs[0].frequency = max_freq;
+       g5_cpu_freqs[1].frequency = max_freq/2;
+
+       /* Check current frequency */
+       g5_pmode_cur = g5_query_freq();
+       if (g5_pmode_cur > 1)
+               /* We don't support anything but 1:1 and 1:2, fixup ... */
+               g5_pmode_cur = 1;
+
+       /* Force apply current frequency to make sure everything is in
+        * sync (voltage is right for example). Firmware may leave us with
+        * a strange setting ...
+        */
+       g5_switch_freq(g5_pmode_cur);
+
+       printk(KERN_INFO "Registering G5 CPU frequency driver\n");
+       printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
+               g5_cpu_freqs[1].frequency/1000,
+               g5_cpu_freqs[0].frequency/1000,
+               g5_cpu_freqs[g5_pmode_cur].frequency/1000);
+
+       rc = cpufreq_register_driver(&g5_cpufreq_driver);
+
+       /* We keep the CPU node on hold... hopefully, Apple G5 don't have
+        * hotplug CPU with a dynamic device-tree ...
+        */
+       return rc;
+
+ bail_noprops:
+       of_node_put(cpunode);
+
+       return rc;
+}
+
+module_init(g5_cpufreq_init);
+
+
+MODULE_LICENSE("GPL");
index 80b58c1ec4120d8b43de70f081d77c2955d56a11..7acb0546671fe2ea341c604573e541bd8d06cad9 100644 (file)
@@ -193,18 +193,6 @@ static void pmac_show_cpuinfo(struct seq_file *m)
                   pmac_newworld ? "NewWorld" : "OldWorld");
 }
 
-static void pmac_show_percpuinfo(struct seq_file *m, int i)
-{
-#ifdef CONFIG_CPU_FREQ_PMAC
-       extern unsigned int pmac_get_one_cpufreq(int i);
-       unsigned int freq = pmac_get_one_cpufreq(i);
-       if (freq != 0) {
-               seq_printf(m, "clock\t\t: %dMHz\n", freq/1000);
-               return;
-       }
-#endif /* CONFIG_CPU_FREQ_PMAC */
-}
-
 #ifndef CONFIG_ADB_CUDA
 int find_via_cuda(void)
 {
@@ -767,7 +755,6 @@ struct machdep_calls __initdata pmac_md = {
        .setup_arch             = pmac_setup_arch,
        .init_early             = pmac_init_early,
        .show_cpuinfo           = pmac_show_cpuinfo,
-       .show_percpuinfo        = pmac_show_percpuinfo,
        .init_IRQ               = pmac_pic_init,
        .get_irq                = mpic_get_irq, /* changed later */
        .pcibios_fixup          = pmac_pcibios_fixup,
index 2130cc31595753643d1db643a57e610ea97265cd..94a81279deaca182ba00768b0727460c7ae99229 100644 (file)
@@ -173,6 +173,16 @@ config KEXEC
          support.  As of this writing the exact hardware interface is
          strongly in flux, so no good recommendation can be made.
 
+source "drivers/cpufreq/Kconfig"
+
+config CPU_FREQ_PMAC64
+       bool "Support for some Apple G5s"
+       depends on CPU_FREQ && PMAC_SMU && PPC64
+       select CPU_FREQ_TABLE
+       help
+         This adds support for frequency switching on Apple iMac G5,
+         and some of the more recent desktop G5 machines as well.
+
 config IBMVIO
        depends on PPC_PSERIES || PPC_ISERIES
        bool
index 077507ffbab80e1601b69e037ccb970d0956f6c6..914632ec587d46fea767a47375160b1b0c2a2ab1 100644 (file)
@@ -560,7 +560,7 @@ _GLOBAL(real_readb)
        isync
        blr
 
-       /*
+/*
  * Do an IO access in real mode
  */
 _GLOBAL(real_writeb)
@@ -592,6 +592,76 @@ _GLOBAL(real_writeb)
        blr
 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
 
+/*
+ * SCOM access functions for 970 (FX only for now)
+ *
+ * unsigned long scom970_read(unsigned int address);
+ * void scom970_write(unsigned int address, unsigned long value);
+ *
+ * The address passed in is the 24 bits register address. This code
+ * is 970 specific and will not check the status bits, so you should
+ * know what you are doing.
+ */
+_GLOBAL(scom970_read)
+       /* interrupts off */
+       mfmsr   r4
+       ori     r0,r4,MSR_EE
+       xori    r0,r0,MSR_EE
+       mtmsrd  r0,1
+
+       /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
+        * (including parity). On current CPUs they must be 0'd,
+        * and finally or in RW bit
+        */
+       rlwinm  r3,r3,8,0,15
+       ori     r3,r3,0x8000
+
+       /* do the actual scom read */
+       sync
+       mtspr   SPRN_SCOMC,r3
+       isync
+       mfspr   r3,SPRN_SCOMD
+       isync
+       mfspr   r0,SPRN_SCOMC
+       isync
+
+       /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
+        * that's the best we can do). Not implemented yet as we don't use
+        * the scom on any of the bogus CPUs yet, but may have to be done
+        * ultimately
+        */
+
+       /* restore interrupts */
+       mtmsrd  r4,1
+       blr
+
+
+_GLOBAL(scom970_write)
+       /* interrupts off */
+       mfmsr   r5
+       ori     r0,r5,MSR_EE
+       xori    r0,r0,MSR_EE
+       mtmsrd  r0,1
+
+       /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
+        * (including parity). On current CPUs they must be 0'd.
+        */
+
+       rlwinm  r3,r3,8,0,15
+
+       sync
+       mtspr   SPRN_SCOMD,r4      /* write data */
+       isync
+       mtspr   SPRN_SCOMC,r3      /* write command */
+       isync
+       mfspr   3,SPRN_SCOMC
+       isync
+
+       /* restore interrupts */
+       mtmsrd  r5,1
+       blr
+
+
 /*
  * Create a kernel thread
  *   kernel_thread(fn, arg, flags)
index 34f3c7e2d832921e783e21e9c22b806d07b71421..a931e508feb65fc64ee4de4e648e5f1ea574bcf5 100644 (file)
@@ -845,6 +845,18 @@ int smu_queue_i2c(struct smu_i2c_cmd *cmd)
        return 0;
 }
 
+struct smu_sdbp_header *smu_get_sdb_partition(int id, unsigned int *size)
+{
+       char pname[32];
+
+       if (!smu)
+               return NULL;
+
+       sprintf(pname, "sdb-partition-%02x", id);
+       return (struct smu_sdbp_header *)get_property(smu->of_node,
+                                                     pname, size);
+}
+EXPORT_SYMBOL(smu_get_sdb_partition);
 
 
 /*
index da848412f11b1dd73d4d72ae672d3cb4a18bcba3..489cf4c99c21470c7856856aa6f4a8c3377a4083 100644 (file)
 #define SPRN_VRSAVE    0x100   /* Vector Register Save Register */
 #define SPRN_XER       0x001   /* Fixed Point Exception Register */
 
+#define SPRN_SCOMC     0x114   /* SCOM Access Control */
+#define SPRN_SCOMD     0x115   /* SCOM Access DATA */
+
 /* Performance monitor SPRs */
 #ifdef CONFIG_PPC64
 #define SPRN_MMCR0     795
@@ -594,7 +597,11 @@ static inline void ppc64_runlatch_off(void)
                mtspr(SPRN_CTRLT, ctrl);
        }
 }
-#endif
+
+extern unsigned long scom970_read(unsigned int address);
+extern void scom970_write(unsigned int address, unsigned long value);
+
+#endif /* CONFIG_PPC64 */
 
 #define __get_SP()     ({unsigned long sp; \
                        asm volatile("mr %0,1": "=r" (sp)); sp;})
index dee8eefe47bc88bc038991527668c170c4e1215c..959bad66023307a54340e4b844dfe6d988a0e049 100644 (file)
  *  - lenght 8 ("VSLEWxyz") has 3 additional bytes appended, and is
  *    used to set the voltage slewing point. The SMU replies with "DONE"
  * I yet have to figure out their exact meaning of those 3 bytes in
- * both cases.
+ * both cases. They seem to be:
+ *  x = processor mask
+ *  y = op. point index
+ *  z = processor freq. step index
+ * I haven't yet decyphered result codes
  *
  */
 #define SMU_CMD_POWER_COMMAND                  0xaa
@@ -333,6 +337,60 @@ extern int smu_queue_i2c(struct smu_i2c_cmd *cmd);
 
 #endif /* __KERNEL__ */
 
+
+/*
+ * - SMU "sdb" partitions informations -
+ */
+
+
+/*
+ * Partition header format
+ */
+struct smu_sdbp_header {
+       __u8    id;
+       __u8    len;
+       __u8    version;
+       __u8    flags;
+};
+
+/*
+ * 32 bits integers are usually encoded with 2x16 bits swapped,
+ * this demangles them
+ */
+#define SMU_U32_MIX(x) ((((x) << 16) & 0xffff0000u) | (((x) >> 16) & 0xffffu))
+
+/* This is the definition of the SMU sdb-partition-0x12 table (called
+ * CPU F/V/T operating points in Darwin). The definition for all those
+ * SMU tables should be moved to some separate file
+ */
+#define SMU_SDB_FVT_ID         0x12
+
+struct smu_sdbp_fvt {
+       __u32   sysclk;                 /* Base SysClk frequency in Hz for
+                                        * this operating point
+                                        */
+       __u8    pad;
+       __u8    maxtemp;                /* Max temp. supported by this
+                                        * operating point
+                                        */
+
+       __u16   volts[3];               /* CPU core voltage for the 3
+                                        * PowerTune modes, a mode with
+                                        * 0V = not supported.
+                                        */
+};
+
+#ifdef __KERNEL__
+/*
+ * This returns the pointer to an SMU "sdb" partition data or NULL
+ * if not found. The data format is described below
+ */
+extern struct smu_sdbp_header *smu_get_sdb_partition(int id,
+                                                    unsigned int *size);
+
+#endif /* __KERNEL__ */
+
+
 /*
  * - Userland interface -
  */