ASoC: SOF: Intel: add PTL specific power control register
authorFred Oh <fred.oh@linux.intel.com>
Fri, 2 Aug 2024 12:40:08 +0000 (14:40 +0200)
committerMark Brown <broonie@kernel.org>
Fri, 2 Aug 2024 13:04:56 +0000 (14:04 +0100)
PTL has some differences from MTL/LNL. Need to use different register
to power up.

Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Fred Oh <fred.oh@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://patch.msgid.link/20240802124011.173820-3-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/sof/intel/mtl.c
sound/soc/sof/intel/mtl.h

index 1bf274509ee62d3c9c4deecc8c741688f4ff4d9d..2b9d22ccf345b86f5b5f9b2a991733d4ba08fe95 100644 (file)
@@ -245,6 +245,18 @@ int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
        u32 cpa;
        u32 pgs;
        int ret;
+       u32 dsppwrctl;
+       u32 dsppwrsts;
+       const struct sof_intel_dsp_desc *chip;
+
+       chip = get_chip_info(sdev->pdata);
+       if (chip->hw_ip_version > SOF_INTEL_ACE_2_0) {
+               dsppwrctl = PTL_HFPWRCTL2;
+               dsppwrsts = PTL_HFPWRSTS2;
+       } else {
+               dsppwrctl = MTL_HFPWRCTL;
+               dsppwrsts = MTL_HFPWRSTS;
+       }
 
        /* Set the DSP subsystem power on */
        snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
@@ -264,14 +276,14 @@ int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
        }
 
        /* Power up gated-DSP-0 domain in order to access the DSP shim register block. */
-       snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
+       snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, dsppwrctl,
                                MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG);
 
        usleep_range(1000, 1010);
 
        /* poll with timeout to check if operation successful */
        pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK;
-       ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFPWRSTS, dsphfpwrsts,
+       ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, dsppwrsts, dsphfpwrsts,
                                            (dsphfpwrsts & pgs) == pgs,
                                            HDA_DSP_REG_POLL_INTERVAL_US,
                                            HDA_DSP_RESET_TIMEOUT_US);
index 7acaa7e724f4420f8a7d067532ec1bc1a2f820bf..9ab4b21c960e2fbdae828b13c8823f8a5b108d85 100644 (file)
 #define MTL_HFDSSCS_CPA_MASK           BIT(24)
 #define MTL_HFSNDWIE                   0x114C
 #define MTL_HFPWRCTL                   0x1D18
+#define PTL_HFPWRCTL2                  0x1D20
 #define MTL_HfPWRCTL_WPIOXPG(x)                BIT((x) + 8)
 #define MTL_HFPWRCTL_WPDSPHPXPG                BIT(0)
 #define MTL_HFPWRSTS                   0x1D1C
+#define PTL_HFPWRSTS2                  0x1D24
 #define MTL_HFPWRSTS_DSPHPXPGS_MASK    BIT(0)
 #define MTL_HFINTIPPTR                 0x1108
 #define MTL_IRQ_INTEN_L_HOST_IPC_MASK  BIT(0)