Merge tag 'kvmarm-fixes-6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git...

KVM/arm64 changes for 6.17, take #2

 - Correctly handle 'invariant' system registers for protected VMs

 - Improved handling of VNCR data aborts, including external aborts

 - Fixes for handling of FEAT_RAS for NV guests, providing a sane
   fault context during SEA injection and preventing the use of
   RASv1p1 fault injection hardware

 - Ensure that page table destruction when a VM is destroyed gives an
   opportunity to reschedule

 - Large fix to KVM's infrastructure for managing guest context loaded
   on the CPU, addressing issues where the output of AT emulation
   doesn't get reflected to the guest

 - Fix AT S12 emulation to actually perform stage-2 translation when
   necessary

 - Avoid attempting vLPI irqbypass when GICv4 has been explicitly
   disabled for a VM

 - Minor KVM + selftest fixes

diff --cc arch/arm64/include/asm/kvm_host.h
Simple merge

diff --cc arch/arm64/include/asm/sysreg.h
Simple merge

diff --cc arch/arm64/kernel/cpufeature.c
Simple merge

diff --cc arch/arm64/kvm/arm.c
Simple merge

diff --cc arch/arm64/kvm/nested.c
Simple merge

diff --cc arch/arm64/kvm/sys_regs.c
index 82ffb3b3b3cf770a94213f4c7bac25487d18453b,cc0dbc45f14494838632812fa8fe18cd360199c1..b29f72478a50d594f3a37ab12bbb5ed9ea901d46
--- 1/arch/arm64/kvm/sys_regs.c
--- 2/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@@ -1606,25 -1733,11 +1733,13 @@@ static u64 __kvm_read_sanitised_id_reg(
                val = sanitise_id_aa64pfr0_el1(vcpu, val);
                break;
        case SYS_ID_AA64PFR1_EL1:
-               if (!kvm_has_mte(vcpu->kvm)) {
-                       val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
-                       val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac);
-               }
- 
-               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);
-               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap);
-               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI);
-               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS);
-               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE);
-               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX);
-               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR);
-               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac);
+               val = sanitise_id_aa64pfr1_el1(vcpu, val);
                break;
        case SYS_ID_AA64PFR2_EL1:
 -              /* We only expose FPMR */
 -              val &= ID_AA64PFR2_EL1_FPMR;
 +              val &= ID_AA64PFR2_EL1_FPMR |
 +                      (kvm_has_mte(vcpu->kvm) ?
 +                       ID_AA64PFR2_EL1_MTEFAR | ID_AA64PFR2_EL1_MTESTOREONLY :
 +                       0);
                break;
        case SYS_ID_AA64ISAR1_EL1:
                if (!vcpu_has_ptrauth(vcpu))
@@@ -2943,12 -3092,8 +3094,11 @@@ static const struct sys_reg_desc sys_re
                                       ID_AA64PFR1_EL1_SME |
                                       ID_AA64PFR1_EL1_RES0 |
                                       ID_AA64PFR1_EL1_MPAM_frac |
-                                      ID_AA64PFR1_EL1_RAS_frac |
                                       ID_AA64PFR1_EL1_MTE)),
 -      ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR),
 +      ID_WRITABLE(ID_AA64PFR2_EL1,
 +                  ID_AA64PFR2_EL1_FPMR |
 +                  ID_AA64PFR2_EL1_MTEFAR |
 +                  ID_AA64PFR2_EL1_MTESTOREONLY),
        ID_UNALLOCATED(4,3),
        ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0),
        ID_HIDDEN(ID_AA64SMFR0_EL1),

diff --cc arch/arm64/tools/cpucaps
Simple merge

diff --cc tools/testing/selftests/kvm/Makefile.kvm
Simple merge

diff --cc tools/testing/selftests/kvm/arm64/debug-exceptions.c
Simple merge