riscv: vector: Fix context save/restore with xtheadvector

Previously only v0-v7 were correctly saved/restored,
and the context of v8-v31 are damanged.
Correctly save/restore v8-v31 to avoid breaking userspace.

Fixes: d863910eabaf ("riscv: vector: Support xtheadvector save/restore")
Cc: stable@vger.kernel.org
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Tested-by: Xiongchuan Tan <tanxiongchuan@isrc.iscas.ac.cn>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Yanteng Si <si.yanteng@linux.dev>
Reviewed-by: Andy Chiu <andybnac@gmail.com>
Link: https://lore.kernel.org/r/9b9eb2337f3d5336ce813721f8ebea51e0b2b553.1747994822.git.rabenda.cn@gmail.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>

diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index 45c9b426fcc52321d55d1a4a42030c3b988e53c0..b61786d43c2054f71727356fa9718b91ec97a38b 100644 (file)
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -205,11 +205,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to,
                        THEAD_VSETVLI_T4X0E8M8D1
                        THEAD_VSB_V_V0T0
                        "add            t0, t0, t4\n\t"
-                       THEAD_VSB_V_V0T0
+                       THEAD_VSB_V_V8T0
                        "add            t0, t0, t4\n\t"
-                       THEAD_VSB_V_V0T0
+                       THEAD_VSB_V_V16T0
                        "add            t0, t0, t4\n\t"
-                       THEAD_VSB_V_V0T0
+                       THEAD_VSB_V_V24T0
                        : : "r" (datap) : "memory", "t0", "t4");
        } else {
                asm volatile (
@@ -241,11 +241,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
                        THEAD_VSETVLI_T4X0E8M8D1
                        THEAD_VLB_V_V0T0
                        "add            t0, t0, t4\n\t"
-                       THEAD_VLB_V_V0T0
+                       THEAD_VLB_V_V8T0
                        "add            t0, t0, t4\n\t"
-                       THEAD_VLB_V_V0T0
+                       THEAD_VLB_V_V16T0
                        "add            t0, t0, t4\n\t"
-                       THEAD_VLB_V_V0T0
+                       THEAD_VLB_V_V24T0
                        : : "r" (datap) : "memory", "t0", "t4");
        } else {
                asm volatile (