clk: x86: Add ST oscout platform clock

Stoney SoC provides oscout clock. This clock can support 25Mhz and
48Mhz of frequency.
The clock is available for general system use.

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

diff --git a/drivers/clk/x86/Makefile b/drivers/clk/x86/Makefile
index 1367afb03858b843e26d265495282237c4887dab..00303bc05415ac0a5b91e1dd059984b0ea9a96b6 100644 (file)
--- a/drivers/clk/x86/Makefile
+++ b/drivers/clk/x86/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_PMC_ATOM)         += clk-pmc-atom.o
+obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE)  += clk-st.o
 clk-x86-lpss-objs              := clk-lpt.o
 obj-$(CONFIG_X86_INTEL_LPSS)   += clk-x86-lpss.o
-obj-$(CONFIG_PMC_ATOM)         += clk-pmc-atom.o

diff --git a/drivers/clk/x86/clk-st.c b/drivers/clk/x86/clk-st.c
new file mode 100644 (file)
index 0000000..fb62f39
--- /dev/null
+++ b/drivers/clk/x86/clk-st.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: MIT
+/*
+ * clock framework for AMD Stoney based clocks
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_data/clk-st.h>
+#include <linux/platform_device.h>
+
+/* Clock Driving Strength 2 register */
+#define CLKDRVSTR2     0x28
+/* Clock Control 1 register */
+#define MISCCLKCNTL1   0x40
+/* Auxiliary clock1 enable bit */
+#define OSCCLKENB      2
+/* 25Mhz auxiliary output clock freq bit */
+#define OSCOUT1CLK25MHZ        16
+
+#define ST_CLK_48M     0
+#define ST_CLK_25M     1
+#define ST_CLK_MUX     2
+#define ST_CLK_GATE    3
+#define ST_MAX_CLKS    4
+
+static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
+static struct clk_hw *hws[ST_MAX_CLKS];
+
+static int st_clk_probe(struct platform_device *pdev)
+{
+       struct st_clk_data *st_data;
+
+       st_data = dev_get_platdata(&pdev->dev);
+       if (!st_data || !st_data->base)
+               return -EINVAL;
+
+       hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0,
+                                                    48000000);
+       hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", NULL, 0,
+                                                    25000000);
+
+       hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
+               clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
+               0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
+
+       clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_25M]->clk);
+
+       hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
+               0, st_data->base + MISCCLKCNTL1, OSCCLKENB,
+               CLK_GATE_SET_TO_DISABLE, NULL);
+
+       clk_hw_register_clkdev(hws[ST_CLK_GATE], "oscout1", NULL);
+
+       return 0;
+}
+
+static int st_clk_remove(struct platform_device *pdev)
+{
+       int i;
+
+       for (i = 0; i < ST_MAX_CLKS; i++)
+               clk_hw_unregister(hws[i]);
+       return 0;
+}
+
+static struct platform_driver st_clk_driver = {
+       .driver = {
+               .name = "clk-st",
+               .suppress_bind_attrs = true,
+       },
+       .probe = st_clk_probe,
+       .remove = st_clk_remove,
+};
+builtin_platform_driver(st_clk_driver);

diff --git a/include/linux/platform_data/clk-st.h b/include/linux/platform_data/clk-st.h
new file mode 100644 (file)
index 0000000..7cdb6a4
--- /dev/null
+++ b/include/linux/platform_data/clk-st.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * clock framework for AMD Stoney based clock
+ *
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ */
+
+#ifndef __CLK_ST_H
+#define __CLK_ST_H
+
+#include <linux/compiler.h>
+
+struct st_clk_data {
+       void __iomem *base;
+};
+
+#endif /* __CLK_ST_H */