LoongArch: Complete KSave registers definition

According to the "LoongArch Reference Manual Volume 1: Basic
Architecture", the KSave registers (SAVE0-SAVE15) are defined in
Section 7.4.16 "Data Save (SAVE)" and listed in Table 7-1 "Control
and Status Registers Overview". These registers occupy the CSR
addresses from 0x30 to 0x3F, with 16 registers in total.

This patch completes the definitions of KS9 to KS15, so as to match
the architecture specification.

Reviewed-by: Wentao Guan <guanwentao@uniontech.com>
Signed-off-by: Yanteng Si <siyanteng@cqsoftware.com.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index a0994d226efff0d8da2a6a84b3c350ccbf9b597f..09dfd7eb406e7e19455064d4d58138dcf9fe905f 100644 (file)
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -451,6 +451,13 @@
 #define LOONGARCH_CSR_KS6              0x36
 #define LOONGARCH_CSR_KS7              0x37
 #define LOONGARCH_CSR_KS8              0x38
+#define LOONGARCH_CSR_KS9              0x39
+#define LOONGARCH_CSR_KS10             0x3a
+#define LOONGARCH_CSR_KS11             0x3b
+#define LOONGARCH_CSR_KS12             0x3c
+#define LOONGARCH_CSR_KS13             0x3d
+#define LOONGARCH_CSR_KS14             0x3e
+#define LOONGARCH_CSR_KS15             0x3f
 
 /* Exception allocated KS0, KS1 and KS2 statically */
 #define EXCEPTION_KS0                  LOONGARCH_CSR_KS0