net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay

There is nothing RX-specific about these clock skew values. So remove
"RX" from the name in preparation for the next patch where TX delays are
also going to be configured.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h
index 25729302714c895ce91852fc4714b44d22be5e36..99e2d20596ad9f0a4d3ec176ebfdc2da6403b45e 100644 (file)
--- a/drivers/net/phy/mscc/mscc.h
+++ b/drivers/net/phy/mscc/mscc.h
@@ -12,15 +12,15 @@
 #include "mscc_macsec.h"
 #endif
 
-enum rgmii_rx_clock_delay {
-       RGMII_RX_CLK_DELAY_0_2_NS = 0,
-       RGMII_RX_CLK_DELAY_0_8_NS = 1,
-       RGMII_RX_CLK_DELAY_1_1_NS = 2,
-       RGMII_RX_CLK_DELAY_1_7_NS = 3,
-       RGMII_RX_CLK_DELAY_2_0_NS = 4,
-       RGMII_RX_CLK_DELAY_2_3_NS = 5,
-       RGMII_RX_CLK_DELAY_2_6_NS = 6,
-       RGMII_RX_CLK_DELAY_3_4_NS = 7
+enum rgmii_clock_delay {
+       RGMII_CLK_DELAY_0_2_NS = 0,
+       RGMII_CLK_DELAY_0_8_NS = 1,
+       RGMII_CLK_DELAY_1_1_NS = 2,
+       RGMII_CLK_DELAY_1_7_NS = 3,
+       RGMII_CLK_DELAY_2_0_NS = 4,
+       RGMII_CLK_DELAY_2_3_NS = 5,
+       RGMII_CLK_DELAY_2_6_NS = 6,
+       RGMII_CLK_DELAY_3_4_NS = 7
 };
 
 /* Microsemi VSC85xx PHY registers */

diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c
index 5d78732de70208af149f22e102cfed7ade819ee7..3aaf03723fa7dfaac0f27fbb6c6a2a63235727a4 100644 (file)
--- a/drivers/net/phy/mscc/mscc_main.c
+++ b/drivers/net/phy/mscc/mscc_main.c
@@ -525,7 +525,7 @@ static int vsc85xx_default_config(struct phy_device *phydev)
        phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
        mutex_lock(&phydev->lock);
 
-       reg_val = RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;
+       reg_val = RGMII_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;
 
        rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
                              MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK,