can: esd_402_pci: Rename esdACC CTRL register macros

Rename macros to use for esdACC CTRL register access to match the
internal documentation and to make the macro prefix consistent.

- ACC_CORE_OF_CTRL_MODE -> ACC_CORE_OF_CTRL
  Makes the name match the documentation.
- ACC_REG_CONTROL_MASK_MODE_ -> ACC_REG_CTRL_MASK_
  ACC_REG_CONTROL_MASK_ -> ACC_REG_CTRL_MASK_
  Makes the prefix consistent for macros describing masks in the same
  register (CTRL).

Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
Link: https://lore.kernel.org/all/20240717214409.3934333-2-stefan.maetje@esd.eu
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>

diff --git a/drivers/net/can/esd/esdacc.c b/drivers/net/can/esd/esdacc.c
index 121cbbf814581d94adf7795567e2318b5debb3d6..ef33d2ccd220079c80e251f013ae87034145801d 100644 (file)
--- a/drivers/net/can/esd/esdacc.c
+++ b/drivers/net/can/esd/esdacc.c
@@ -43,8 +43,8 @@
 
 static void acc_resetmode_enter(struct acc_core *core)
 {
-       acc_set_bits(core, ACC_CORE_OF_CTRL_MODE,
-                    ACC_REG_CONTROL_MASK_MODE_RESETMODE);
+       acc_set_bits(core, ACC_CORE_OF_CTRL,
+                    ACC_REG_CTRL_MASK_RESETMODE);
 
        /* Read back reset mode bit to flush PCI write posting */
        acc_resetmode_entered(core);
@@ -52,8 +52,8 @@ static void acc_resetmode_enter(struct acc_core *core)
 
 static void acc_resetmode_leave(struct acc_core *core)
 {
-       acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE,
-                      ACC_REG_CONTROL_MASK_MODE_RESETMODE);
+       acc_clear_bits(core, ACC_CORE_OF_CTRL,
+                      ACC_REG_CTRL_MASK_RESETMODE);
 
        /* Read back reset mode bit to flush PCI write posting */
        acc_resetmode_entered(core);
@@ -172,7 +172,7 @@ int acc_open(struct net_device *netdev)
        struct acc_net_priv *priv = netdev_priv(netdev);
        struct acc_core *core = priv->core;
        u32 tx_fifo_status;
-       u32 ctrl_mode;
+       u32 ctrl;
        int err;
 
        /* Retry to enter RESET mode if out of sync. */
@@ -187,19 +187,19 @@ int acc_open(struct net_device *netdev)
        if (err)
                return err;
 
-       ctrl_mode = ACC_REG_CONTROL_MASK_IE_RXTX |
-                       ACC_REG_CONTROL_MASK_IE_TXERROR |
-                       ACC_REG_CONTROL_MASK_IE_ERRWARN |
-                       ACC_REG_CONTROL_MASK_IE_OVERRUN |
-                       ACC_REG_CONTROL_MASK_IE_ERRPASS;
+       ctrl = ACC_REG_CTRL_MASK_IE_RXTX |
+               ACC_REG_CTRL_MASK_IE_TXERROR |
+               ACC_REG_CTRL_MASK_IE_ERRWARN |
+               ACC_REG_CTRL_MASK_IE_OVERRUN |
+               ACC_REG_CTRL_MASK_IE_ERRPASS;
 
        if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
-               ctrl_mode |= ACC_REG_CONTROL_MASK_IE_BUSERR;
+               ctrl |= ACC_REG_CTRL_MASK_IE_BUSERR;
 
        if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
-               ctrl_mode |= ACC_REG_CONTROL_MASK_MODE_LOM;
+               ctrl |= ACC_REG_CTRL_MASK_LOM;
 
-       acc_set_bits(core, ACC_CORE_OF_CTRL_MODE, ctrl_mode);
+       acc_set_bits(core, ACC_CORE_OF_CTRL, ctrl);
 
        acc_resetmode_leave(core);
        priv->can.state = CAN_STATE_ERROR_ACTIVE;
@@ -218,13 +218,13 @@ int acc_close(struct net_device *netdev)
        struct acc_net_priv *priv = netdev_priv(netdev);
        struct acc_core *core = priv->core;
 
-       acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE,
-                      ACC_REG_CONTROL_MASK_IE_RXTX |
-                      ACC_REG_CONTROL_MASK_IE_TXERROR |
-                      ACC_REG_CONTROL_MASK_IE_ERRWARN |
-                      ACC_REG_CONTROL_MASK_IE_OVERRUN |
-                      ACC_REG_CONTROL_MASK_IE_ERRPASS |
-                      ACC_REG_CONTROL_MASK_IE_BUSERR);
+       acc_clear_bits(core, ACC_CORE_OF_CTRL,
+                      ACC_REG_CTRL_MASK_IE_RXTX |
+                      ACC_REG_CTRL_MASK_IE_TXERROR |
+                      ACC_REG_CTRL_MASK_IE_ERRWARN |
+                      ACC_REG_CTRL_MASK_IE_OVERRUN |
+                      ACC_REG_CTRL_MASK_IE_ERRPASS |
+                      ACC_REG_CTRL_MASK_IE_BUSERR);
 
        netif_stop_queue(netdev);
        acc_resetmode_enter(core);
@@ -233,9 +233,9 @@ int acc_close(struct net_device *netdev)
        /* Mark pending TX requests to be aborted after controller restart. */
        acc_write32(core, ACC_CORE_OF_TX_ABORT_MASK, 0xffff);
 
-       /* ACC_REG_CONTROL_MASK_MODE_LOM is only accessible in RESET mode */
-       acc_clear_bits(core, ACC_CORE_OF_CTRL_MODE,
-                      ACC_REG_CONTROL_MASK_MODE_LOM);
+       /* ACC_REG_CTRL_MASK_LOM is only accessible in RESET mode */
+       acc_clear_bits(core, ACC_CORE_OF_CTRL,
+                      ACC_REG_CTRL_MASK_LOM);
 
        close_candev(netdev);
        return 0;

diff --git a/drivers/net/can/esd/esdacc.h b/drivers/net/can/esd/esdacc.h
index a70488b25d3905948f5031807b25ecf16385736c..d13dfa60703a108bad8b4b19d474a7c2a3833e21 100644 (file)
--- a/drivers/net/can/esd/esdacc.h
+++ b/drivers/net/can/esd/esdacc.h
@@ -50,7 +50,7 @@
 #define ACC_OV_REG_MODE_MASK_FPGA_RESET BIT(31)
 
 /* esdACC CAN Core Module */
-#define ACC_CORE_OF_CTRL_MODE 0x0000
+#define ACC_CORE_OF_CTRL 0x0000
 #define ACC_CORE_OF_STATUS_IRQ 0x0008
 #define ACC_CORE_OF_BRP        0x000c
 #define ACC_CORE_OF_BTR        0x0010
@@ -66,21 +66,22 @@
 #define ACC_CORE_OF_TXFIFO_DATA_0 0x00c8
 #define ACC_CORE_OF_TXFIFO_DATA_1 0x00cc
 
-#define ACC_REG_CONTROL_MASK_MODE_RESETMODE BIT(0)
-#define ACC_REG_CONTROL_MASK_MODE_LOM BIT(1)
-#define ACC_REG_CONTROL_MASK_MODE_STM BIT(2)
-#define ACC_REG_CONTROL_MASK_MODE_TRANSEN BIT(5)
-#define ACC_REG_CONTROL_MASK_MODE_TS BIT(6)
-#define ACC_REG_CONTROL_MASK_MODE_SCHEDULE BIT(7)
-
-#define ACC_REG_CONTROL_MASK_IE_RXTX BIT(8)
-#define ACC_REG_CONTROL_MASK_IE_TXERROR BIT(9)
-#define ACC_REG_CONTROL_MASK_IE_ERRWARN BIT(10)
-#define ACC_REG_CONTROL_MASK_IE_OVERRUN BIT(11)
-#define ACC_REG_CONTROL_MASK_IE_TSI BIT(12)
-#define ACC_REG_CONTROL_MASK_IE_ERRPASS BIT(13)
-#define ACC_REG_CONTROL_MASK_IE_ALI BIT(14)
-#define ACC_REG_CONTROL_MASK_IE_BUSERR BIT(15)
+/* CTRL register layout */
+#define ACC_REG_CTRL_MASK_RESETMODE BIT(0)
+#define ACC_REG_CTRL_MASK_LOM BIT(1)
+#define ACC_REG_CTRL_MASK_STM BIT(2)
+#define ACC_REG_CTRL_MASK_TRANSEN BIT(5)
+#define ACC_REG_CTRL_MASK_TS BIT(6)
+#define ACC_REG_CTRL_MASK_SCHEDULE BIT(7)
+
+#define ACC_REG_CTRL_MASK_IE_RXTX BIT(8)
+#define ACC_REG_CTRL_MASK_IE_TXERROR BIT(9)
+#define ACC_REG_CTRL_MASK_IE_ERRWARN BIT(10)
+#define ACC_REG_CTRL_MASK_IE_OVERRUN BIT(11)
+#define ACC_REG_CTRL_MASK_IE_TSI BIT(12)
+#define ACC_REG_CTRL_MASK_IE_ERRPASS BIT(13)
+#define ACC_REG_CTRL_MASK_IE_ALI BIT(14)
+#define ACC_REG_CTRL_MASK_IE_BUSERR BIT(15)
 
 /* BRP and BTR register layout for CAN-Classic version */
 #define ACC_REG_BRP_CL_MASK_BRP GENMASK(8, 0)
@@ -300,9 +301,9 @@ static inline void acc_clear_bits(struct acc_core *core,
 
 static inline int acc_resetmode_entered(struct acc_core *core)
 {
-       u32 ctrl = acc_read32(core, ACC_CORE_OF_CTRL_MODE);
+       u32 ctrl = acc_read32(core, ACC_CORE_OF_CTRL);
 
-       return (ctrl & ACC_REG_CONTROL_MASK_MODE_RESETMODE) != 0;
+       return (ctrl & ACC_REG_CTRL_MASK_RESETMODE) != 0;
 }
 
 static inline u32 acc_ov_read32(struct acc_ov *ov, unsigned short offs)