arm64: dts: qcom: ipq5018: enable the CPUFreq support

Add the APCS, A53 PLL, cpu-opp-table nodes to set
the CPU frequency at 800MHz (idle) or 1.008GHz.

Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230925102826.405446-4-quic_gokulsri@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 0b739077ed707920d1a9b767852fd551fda01eec..ae31bd72f0b739e5e204031e8ba0264f911fdf8f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -5,6 +5,7 @@
  * Copyright (c) 2023 The Linux Foundation. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,apss-ipq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
@@ -36,6 +37,8 @@
                        reg = <0x0>;
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
+                       clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+                       operating-points-v2 = <&cpu_opp_table>;
                };
 
                CPU1: cpu@1 {
@@ -44,6 +47,8 @@
                        reg = <0x1>;
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
+                       clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+                       operating-points-v2 = <&cpu_opp_table>;
                };
 
                L2_0: l2-cache {
@@ -54,6 +59,23 @@
                };
        };
 
+       cpu_opp_table: opp-table-cpu {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <200000>;
+               };
+
+               opp-1008000000 {
+                       opp-hz = /bits/ 64 <1008000000>;
+                       opp-microvolt = <1100000>;
+                       clock-latency-ns = <200000>;
+               };
+       };
+
        firmware {
                scm {
                        compatible = "qcom,scm-ipq5018", "qcom,scm";
@@ -267,6 +289,24 @@
                        clocks = <&sleep_clk>;
                };
 
+               apcs_glb: mailbox@b111000 {
+                       compatible = "qcom,ipq5018-apcs-apps-global",
+                                    "qcom,ipq6018-apcs-apps-global";
+                       reg = <0x0b111000 0x1000>;
+                       #clock-cells = <1>;
+                       clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
+                       clock-names = "pll", "xo", "gpll0";
+                       #mbox-cells = <1>;
+               };
+
+               a53pll: clock@b116000 {
+                       compatible = "qcom,ipq5018-a53pll";
+                       reg = <0x0b116000 0x40>;
+                       #clock-cells = <0>;
+                       clocks = <&xo_board_clk>;
+                       clock-names = "xo";
+               };
+
                timer@b120000 {
                        compatible = "arm,armv7-timer-mem";
                        reg = <0x0b120000 0x1000>;