Revert "drm/amdgpu: add vcn_v5_0 ip dump support"

This reverts commit a46a7bef7d41ee7787c246f47a656fbafe02f122.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 6e6eaf2358d201d5d70f8bc13f615c68b0f52b40..68c97fcd539b9028be59b96b1feffdc6b6dd9d2e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -37,134 +37,6 @@
 
 #include <drm/drm_drv.h>
 
-static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0[] = {
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_IPX_DLDO_CONFIG),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_IPX_DLDO_STATUS),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
-       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
-};
-
 static int amdgpu_ih_clientid_vcns[] = {
        SOC15_IH_CLIENTID_VCN,
        SOC15_IH_CLIENTID_VCN1
@@ -211,8 +83,6 @@ static int vcn_v5_0_0_sw_init(void *handle)
        struct amdgpu_ring *ring;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        int i, r;
-       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
-       uint32_t *ptr;
 
        r = amdgpu_vcn_sw_init(adev);
        if (r)
@@ -267,14 +137,6 @@ static int vcn_v5_0_0_sw_init(void *handle)
        if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
                adev->vcn.pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode;
 
-       /* Allocate memory for VCN IP Dump buffer */
-       ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
-       if (!ptr) {
-               DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
-               adev->vcn.ip_dump = NULL;
-       } else {
-               adev->vcn.ip_dump = ptr;
-       }
        return 0;
 }
 
@@ -311,8 +173,6 @@ static int vcn_v5_0_0_sw_fini(void *handle)
 
        r = amdgpu_vcn_sw_fini(adev);
 
-       kfree(adev->vcn.ip_dump);
-
        return r;
 }
 
@@ -1437,34 +1297,6 @@ static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev)
        }
 }
 
-static void vcn_v5_0_dump_ip_state(void *handle)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-       int i, j;
-       bool is_powered;
-       uint32_t inst_off;
-       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
-
-       if (!adev->vcn.ip_dump)
-               return;
-
-       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-               if (adev->vcn.harvest_config & (1 << i))
-                       continue;
-
-               inst_off = i * reg_count;
-               /* mmUVD_POWER_STATUS is always readable and is first element of the array */
-               adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
-               is_powered = (adev->vcn.ip_dump[inst_off] &
-                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
-
-               if (is_powered)
-                       for (j = 1; j < reg_count; j++)
-                               adev->vcn.ip_dump[inst_off + j] =
-                                       RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i));
-       }
-}
-
 static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
        .name = "vcn_v5_0_0",
        .early_init = vcn_v5_0_0_early_init,
@@ -1483,7 +1315,7 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
        .post_soft_reset = NULL,
        .set_clockgating_state = vcn_v5_0_0_set_clockgating_state,
        .set_powergating_state = vcn_v5_0_0_set_powergating_state,
-       .dump_ip_state = vcn_v5_0_dump_ip_state,
+       .dump_ip_state = NULL,
        .print_ip_state = NULL,
 };