irqchip/gic-v4: Enable low-level GICv4 operations
authorMarc Zyngier <marc.zyngier@arm.com>
Tue, 20 Dec 2016 15:31:54 +0000 (15:31 +0000)
committerMarc Zyngier <marc.zyngier@arm.com>
Thu, 31 Aug 2017 14:31:42 +0000 (15:31 +0100)
Get the show on the road...

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
drivers/irqchip/Makefile
drivers/irqchip/irq-gic-v3-its.c
drivers/irqchip/irq-gic-v4.c
include/linux/irqchip/arm-gic-v4.h

index 2c630574986ff3da5ed693ce1cc9b8c2de10dda9..845abc107ad5f05e0b85fe5325a05e216f6f9817 100644 (file)
@@ -28,7 +28,7 @@ obj-$(CONFIG_ARM_GIC_PM)              += irq-gic-pm.o
 obj-$(CONFIG_ARCH_REALVIEW)            += irq-gic-realview.o
 obj-$(CONFIG_ARM_GIC_V2M)              += irq-gic-v2m.o
 obj-$(CONFIG_ARM_GIC_V3)               += irq-gic-v3.o irq-gic-common.o
-obj-$(CONFIG_ARM_GIC_V3_ITS)           += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o
+obj-$(CONFIG_ARM_GIC_V3_ITS)           += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o irq-gic-v4.o
 obj-$(CONFIG_PARTITION_PERCPU)         += irq-partition-percpu.o
 obj-$(CONFIG_HISILICON_IRQ_MBIGEN)     += irq-mbigen.o
 obj-$(CONFIG_ARM_NVIC)                 += irq-nvic.o
index d79bfdbd506bd91a787fde1de839ba2bd2f6649a..a93816cb2a98a89d8ca03f868cfbc0a7a1ca3737 100644 (file)
@@ -3226,7 +3226,8 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
                has_v4 |= its->is_v4;
 
        if (has_v4 & rdists->has_vlpis) {
-               if (its_init_vpe_domain()) {
+               if (its_init_vpe_domain() ||
+                   its_init_v4(parent_domain, &its_vpe_domain_ops)) {
                        rdists->has_vlpis = false;
                        pr_err("ITS: Disabling GICv4 support\n");
                }
index 8eb2ad39322eb74717c32def4bd8fca65872a4ef..2370e6d9e603ad17a57016974608b8aade9f85a2 100644 (file)
@@ -210,3 +210,16 @@ int its_prop_update_vlpi(int irq, u8 config, bool inv)
 
        return irq_set_vcpu_affinity(irq, &info);
 }
+
+int its_init_v4(struct irq_domain *domain, const struct irq_domain_ops *ops)
+{
+       if (domain) {
+               pr_info("ITS: Enabling GICv4 support\n");
+               gic_domain = domain;
+               vpe_domain_ops = ops;
+               return 0;
+       }
+
+       pr_err("ITS: No GICv4 VPE domain allocated\n");
+       return -ENODEV;
+}
index e22f878ad01703e27491bf251594452ae725c0a6..58a4d89aa82c022644ac371bdfa64ecedcd5ee26 100644 (file)
@@ -100,4 +100,6 @@ int its_get_vlpi(int irq, struct its_vlpi_map *map);
 int its_unmap_vlpi(int irq);
 int its_prop_update_vlpi(int irq, u8 config, bool inv);
 
+int its_init_v4(struct irq_domain *domain, const struct irq_domain_ops *ops);
+
 #endif