drm/amd/display: access hpo dp link encoder only through link resource

[why]
Update all accesses to use hpo dp link encoder through link resource
only.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index a394946ef5132481b51703fcc8c654684db366a4..9197dd73c6d2b157be22ecd9a43096f0d07780ca 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3426,7 +3426,7 @@ static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
 {
        struct dc_stream_state *stream = pipe_ctx->stream;
        struct dc_link *link = stream->link;
-       struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
+       struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
        struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
        struct link_mst_stream_allocation_table proposed_table = {0};
        struct fixed31_32 avg_time_slots_per_mtp;
@@ -3508,7 +3508,7 @@ enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
        struct link_encoder *link_encoder = NULL;
        struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-       struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
+       struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
        struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
 #endif
        struct dp_mst_stream_allocation_table proposed_table = {0};
@@ -3838,7 +3838,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
        struct link_encoder *link_encoder = NULL;
        struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-       struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
+       struct hpo_dp_link_encoder *hpo_dp_link_encoder = pipe_ctx->link_res.hpo_dp_link_enc;
        struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
 #endif
        struct dp_mst_stream_allocation_table proposed_table = {0};
@@ -4164,12 +4164,12 @@ static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pi
                proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
        }
 
-       stream->link->hpo_dp_link_enc->funcs->update_stream_allocation_table(
-                       stream->link->hpo_dp_link_enc,
+       pipe_ctx->link_res.hpo_dp_link_enc->funcs->update_stream_allocation_table(
+                       pipe_ctx->link_res.hpo_dp_link_enc,
                        &proposed_table);
 
-       stream->link->hpo_dp_link_enc->funcs->set_throttled_vcp_size(
-                       stream->link->hpo_dp_link_enc,
+       pipe_ctx->link_res.hpo_dp_link_enc->funcs->set_throttled_vcp_size(
+                       pipe_ctx->link_res.hpo_dp_link_enc,
                        pipe_ctx->stream_res.hpo_dp_stream_enc->inst,
                        avg_time_slots_per_mtp);
 
@@ -4674,11 +4674,9 @@ void dc_link_set_preferred_training_settings(struct dc *dc,
        if (link_setting != NULL) {
                link->preferred_link_setting = *link_setting;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-               if (dp_get_link_encoding_format(link_setting) ==
-                               DP_128b_132b_ENCODING && !link->hpo_dp_link_enc) {
-                       if (!add_dp_hpo_link_encoder_to_link(link))
-                               memset(&link->preferred_link_setting, 0, sizeof(link->preferred_link_setting));
-               }
+               if (dp_get_link_encoding_format(link_setting) == DP_128b_132b_ENCODING)
+                       /* TODO: add dc update for acquiring link res  */
+                       skip_immediate_retrain = true;
 #endif
        } else {
                link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 98835d6c90360086017f8bd9b8a09e3de1fdaec3..05e216524370d4099211cdd9b4b571da7a410c94 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3211,9 +3211,11 @@ static struct dc_link_settings get_max_link_cap(struct dc_link *link,
        if (link_enc)
                link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap);
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-       if (max_link_cap.link_rate >= LINK_RATE_UHBR10 &&
-                       !link->hpo_dp_link_enc)
-               max_link_cap.link_rate = LINK_RATE_HIGH3;
+       if (max_link_cap.link_rate >= LINK_RATE_UHBR10) {
+               if (!link_res->hpo_dp_link_enc ||
+                               link->dc->debug.disable_uhbr)
+                       max_link_cap.link_rate = LINK_RATE_HIGH3;
+       }
 #endif
 
        /* Lower link settings based on sink's link cap */
@@ -7016,8 +7018,10 @@ struct fixed31_32 calculate_sst_avg_time_slots_per_mtp(
 
 bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx)
 {
+       /* If this assert is hit then we have a link encoder dynamic management issue */
+       ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
        return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
-                       pipe_ctx->stream->link->hpo_dp_link_enc &&
+                       pipe_ctx->link_res.hpo_dp_link_enc &&
                        dc_is_dp_signal(pipe_ctx->stream->signal));
 }
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 10d7f986011d53792f9bc79ffb12f2790188d5e5..dd69e8f22e75ab6b871e01b2fa0e61b06595570d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -243,7 +243,7 @@ void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_
        struct dc  *dc = link->ctx->dc;
        struct dmcu *dmcu = dc->res_pool->dmcu;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-       struct hpo_dp_link_encoder *hpo_link_enc = link->hpo_dp_link_enc;
+       struct hpo_dp_link_encoder *hpo_link_enc = link_res->hpo_dp_link_enc;
 #endif
        struct link_encoder *link_enc;
 
@@ -366,8 +366,8 @@ void dp_set_hw_lane_settings(
 #if defined(CONFIG_DRM_AMD_DC_DCN)
        if (dp_get_link_encoding_format(&link_settings->link_settings) ==
                        DP_128b_132b_ENCODING) {
-               link->hpo_dp_link_enc->funcs->set_ffe(
-                               link->hpo_dp_link_enc,
+               link_res->hpo_dp_link_enc->funcs->set_ffe(
+                               link_res->hpo_dp_link_enc,
                                &link_settings->link_settings,
                                link_settings->lane_settings[0].FFE_PRESET.raw);
        } else if (dp_get_link_encoding_format(&link_settings->link_settings)
@@ -412,8 +412,8 @@ void dp_set_hw_test_pattern(
 #if defined(CONFIG_DRM_AMD_DC_DCN)
        switch (link_encoding_format) {
        case DP_128b_132b_ENCODING:
-               link->hpo_dp_link_enc->funcs->set_link_test_pattern(
-                               link->hpo_dp_link_enc, &pattern_param);
+               link_res->hpo_dp_link_enc->funcs->set_link_test_pattern(
+                               link_res->hpo_dp_link_enc, &pattern_param);
                break;
        case DP_8b_10b_ENCODING:
                ASSERT(encoder);
@@ -797,8 +797,8 @@ void enable_dp_hpo_output(struct dc_link *link,
                }
        } else {
                /* DP2.0 HW: call transmitter control to enable PHY */
-               link->hpo_dp_link_enc->funcs->enable_link_phy(
-                               link->hpo_dp_link_enc,
+               link_res->hpo_dp_link_enc->funcs->enable_link_phy(
+                               link_res->hpo_dp_link_enc,
                                link_settings,
                                link->link_enc->transmitter);
        }
@@ -814,11 +814,11 @@ void enable_dp_hpo_output(struct dc_link *link,
                phyd32clk = get_phyd32clk_src(link);
                dc->res_pool->dccg->funcs->enable_symclk32_le(
                                dc->res_pool->dccg,
-                               link->hpo_dp_link_enc->inst,
+                               link_res->hpo_dp_link_enc->inst,
                                phyd32clk);
-               link->hpo_dp_link_enc->funcs->link_enable(
-                                       link->hpo_dp_link_enc,
-                                       link_settings->lane_count);
+               link_res->hpo_dp_link_enc->funcs->link_enable(
+                               link_res->hpo_dp_link_enc,
+                               link_settings->lane_count);
        }
 }
 
@@ -828,12 +828,12 @@ void disable_dp_hpo_output(struct dc_link *link,
 {
        const struct dc *dc = link->dc;
 
-       link->hpo_dp_link_enc->funcs->link_disable(link->hpo_dp_link_enc);
+       link_res->hpo_dp_link_enc->funcs->link_disable(link_res->hpo_dp_link_enc);
 
        if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
                dc->res_pool->dccg->funcs->disable_symclk32_le(
                                        dc->res_pool->dccg,
-                                       link->hpo_dp_link_enc->inst);
+                                       link_res->hpo_dp_link_enc->inst);
 
                dc->res_pool->dccg->funcs->set_physymclk(
                                        dc->res_pool->dccg,
@@ -844,8 +844,8 @@ void disable_dp_hpo_output(struct dc_link *link,
                dm_set_phyd32clk(dc->ctx, 0);
        } else {
                /* DP2.0 HW: call transmitter control to disable PHY */
-               link->hpo_dp_link_enc->funcs->disable_link_phy(
-                               link->hpo_dp_link_enc,
+               link_res->hpo_dp_link_enc->funcs->disable_link_phy(
+                               link_res->hpo_dp_link_enc,
                                signal);
        }
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 1be74d6223dfb411f1d8b549392064e7d2d9eb40..288e7b01f56174cbcb33932a3f5a8d6d5928a448 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -691,6 +691,7 @@ struct dc_debug_options {
        /* TODO - remove once tested */
        bool legacy_dp2_lt;
        bool set_mst_en_for_sst;
+       bool disable_uhbr;
        bool force_dp2_lt_fallback_method;
 #endif
        union mem_low_power_enable_options enable_mem_low_power;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 2d470f52436718628a4055ba99c9828088ad3a3f..f19015413ce311c1fc1ff0372a70e163db9bbcb8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -468,8 +468,6 @@ void dcn10_log_hw_state(struct dc *dc,
        log_mpc_crc(dc, log_ctx);
 
        {
-               int hpo_dp_link_enc_count = 0;
-
                if (pool->hpo_dp_stream_enc_count > 0) {
                        DTN_INFO("DP HPO S_ENC:  Enabled  OTG   Format   Depth   Vid   SDP   Compressed  Link\n");
                        for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
@@ -500,18 +498,14 @@ void dcn10_log_hw_state(struct dc *dc,
                }
 
                /* log DP HPO L_ENC section if any hpo_dp_link_enc exists */
-               for (i = 0; i < dc->link_count; i++)
-                       if (dc->links[i]->hpo_dp_link_enc)
-                               hpo_dp_link_enc_count++;
-
-               if (hpo_dp_link_enc_count) {
+               if (pool->hpo_dp_link_enc_count) {
                        DTN_INFO("DP HPO L_ENC:  Enabled  Mode   Lanes   Stream  Slots   VC Rate X    VC Rate Y\n");
 
-                       for (i = 0; i < dc->link_count; i++) {
-                               struct hpo_dp_link_encoder *hpo_dp_link_enc = dc->links[i]->hpo_dp_link_enc;
+                       for (i = 0; i < pool->hpo_dp_link_enc_count; i++) {
+                               struct hpo_dp_link_encoder *hpo_dp_link_enc = pool->hpo_dp_link_enc[i];
                                struct hpo_dp_link_enc_state hpo_dp_le_state = {0};
 
-                               if (hpo_dp_link_enc && hpo_dp_link_enc->funcs->read_state) {
+                               if (hpo_dp_link_enc->funcs->read_state) {
                                        hpo_dp_link_enc->funcs->read_state(hpo_dp_link_enc, &hpo_dp_le_state);
                                        DTN_INFO("[%d]:                 %d  %6s     %d        %d      %d     %d     %d\n",
                                                        hpo_dp_link_enc->inst,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index a17fe8ab290400a35d617771c99035582fcb9d91..4991e93e5308c5175f7d1aabd272501688b24bb2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2414,7 +2414,7 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
                pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->map_stream_to_link(
                                pipe_ctx->stream_res.hpo_dp_stream_enc,
                                pipe_ctx->stream_res.hpo_dp_stream_enc->inst,
-                               link->hpo_dp_link_enc->inst);
+                               pipe_ctx->link_res.hpo_dp_link_enc->inst);
        }
 
        if (!is_dp_128b_132b_signal(pipe_ctx) && link_enc)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
index 91810aaee5a337ba4b54d5a3bcccb47b33b53092..789f7562cdc75efcee5b52dd2b1e08674209d5c5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_wrapper.c
@@ -1274,7 +1274,7 @@ static void dcn20_adjust_adaptive_sync_v_startup(
 static bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx)
 {
        return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
-                       pipe_ctx->stream->link->hpo_dp_link_enc &&
+                       pipe_ctx->link_res.hpo_dp_link_enc &&
                        dc_is_dp_signal(pipe_ctx->stream->signal));
 }