KVM: arm64: nv: Truely enable nXS TLBI operations

Although we now have support for nXS-flavoured TLBI instructions,
we still don't expose the feature to the guest thanks to a mixture
of misleading comment and use of a bunch of magic values.

Fix the comment and correctly express the masking of LS64, which
is enough to expose nXS to the world. Not that anyone cares...

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240703154743.824824-1-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
index 451926cb6c5d7d2308dde3d324757636f3c811d7..4b51d7a59c2def760193fc7952eee2cb80190cb3 100644 (file)
--- a/arch/arm64/kvm/nested.c
+++ b/arch/arm64/kvm/nested.c
@@ -810,8 +810,8 @@ static u64 limit_nv_id_reg(u32 id, u64 val)
                break;
 
        case SYS_ID_AA64ISAR1_EL1:
-               /* Support everything but Spec Invalidation */
-               val &= ~(GENMASK_ULL(63, 56)    |
+               /* Support everything but Spec Invalidation and LS64 */
+               val &= ~(NV_FTR(ISAR1, LS64)    |
                         NV_FTR(ISAR1, SPECRES));
                break;