drm/amdgpu: fix bug mclk can't change on Polaris
authorRex Zhu <Rex.Zhu@amd.com>
Wed, 23 Nov 2016 10:09:22 +0000 (18:09 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 6 Dec 2016 23:08:23 +0000 (18:08 -0500)
the root cause is we gate the clock to uvd vcpu.
mclk's change should need the response from uvd if
it is power on.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

index 95cabeafc18ebe47a8eb0932ef5c15a53001ff57..a79e283590fbe7fc9b627a097ccec81b99d1a66c 100644 (file)
@@ -640,7 +640,7 @@ static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
                     UVD_SUVD_CGC_GATE__SDB_MASK;
 
        if (enable) {
-               data3 |= (UVD_CGC_GATE__SYS_MASK       |
+               data3 |= (UVD_CGC_GATE__SYS_MASK     |
                        UVD_CGC_GATE__UDEC_MASK      |
                        UVD_CGC_GATE__MPEG2_MASK     |
                        UVD_CGC_GATE__RBC_MASK       |
@@ -656,9 +656,11 @@ static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
                        UVD_CGC_GATE__UDEC_DB_MASK   |
                        UVD_CGC_GATE__UDEC_MP_MASK   |
                        UVD_CGC_GATE__WCB_MASK       |
-                       UVD_CGC_GATE__VCPU_MASK      |
                        UVD_CGC_GATE__JPEG_MASK      |
                        UVD_CGC_GATE__SCPU_MASK);
+               /* only in pg enabled, we can gate clock to vcpu*/
+               if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
+                       data3 |= UVD_CGC_GATE__VCPU_MASK;
                data3 &= ~UVD_CGC_GATE__REGS_MASK;
                data1 |= suvd_flags;
        } else {
index c697a73b872b9d6eb24ab1031a33db5b78fe7175..ba0bbf7138dca29dee3be523045e62f953de585f 100644 (file)
@@ -879,10 +879,13 @@ static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
                        UVD_CGC_GATE__UDEC_DB_MASK   |
                        UVD_CGC_GATE__UDEC_MP_MASK   |
                        UVD_CGC_GATE__WCB_MASK       |
-                       UVD_CGC_GATE__VCPU_MASK      |
                        UVD_CGC_GATE__JPEG_MASK      |
                        UVD_CGC_GATE__SCPU_MASK      |
                        UVD_CGC_GATE__JPEG2_MASK);
+               /* only in pg enabled, we can gate clock to vcpu*/
+               if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
+                       data3 |= UVD_CGC_GATE__VCPU_MASK;
+
                data3 &= ~UVD_CGC_GATE__REGS_MASK;
        } else {
                data3 = 0;