Merge tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.4 kernel cycle:

  Core changes:

   - Fix errors in example code in the documentation.

  New drivers:

   - Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to the
     Ingenic driver.

   - Support Cirrus Logic Madera CS47L92 and CS47L15.

   - Support Allwinner Sunxi V3S.

   - Support Aspeed 2600 BMC.

   - Support Qualcomm SC7180.

   - Support Marvell MVEBU CS115.

  Driver improvements:

   - Clean up a few drivers to use the devm_platform_ioremap_resource()
     helper.

   - Pass the irqchip when registering the gpio_chip in some pin
     controllers that are also GPIO controllers.

   - Support suspend/resume in the Tegra driver.

   - Support pull-up on the Broadcom BCM2711.

   - The Intel driver can now request locked pads.

   - Fix the UFS reset pin in the Qualcomm SDM845 driver"

* tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits)
  pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c
  pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()
  pinctrl: bcm: remove redundant assignment to pointer log
  pinctrl: iproc: Add 'get_direction' support
  pinctrl: iproc-gpio: Handle interrupts for multiple instances
  pinctrl: iproc-gpio: Fix incorrect pinconf configurations
  pinctrl: intel: mark intel_pin_to_gpio __maybe_unused
  pinctrl: qcom: sdm845: Fix UFS_RESET pin
  pinctrl: mvebu: add additional variant for standalone CP115
  pinctrl: mvebu: Add CP110 missing pin functionality
  dt-bindings: cp110: document the new CP115 pinctrl compatible
  pinctrl: bcm2835: Pass irqchip when adding gpiochip
  pinctrl: meson: meson: Add of_node_put() before return
  pinctrl/gpio: Take MUX usage into account
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support
  pinctrl: amd: disable spurious-firing GPIO IRQs
  pinctrl: rza2: Include the appropriate headers
  pinctrl: rza2: Drop driver use of consumer flags
  ...

diff --combined drivers/gpio/gpiolib.c
index 822988818efcb201926344e77de9724076a4b232,52937bf8e5140052afd33ff6de057a29cb86f0ea..bdbc1649eafa26ed18f0d9f3058399fce5345a2c
--- 1/drivers/gpio/gpiolib.c
--- 2/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@@ -11,6 -11,7 +11,6 @@@
  #include <linux/debugfs.h>
  #include <linux/seq_file.h>
  #include <linux/gpio.h>
 -#include <linux/of_gpio.h>
  #include <linux/idr.h>
  #include <linux/slab.h>
  #include <linux/acpi.h>
@@@ -29,8 -30,6 +29,8 @@@
  #include <uapi/linux/gpio.h>
  
  #include "gpiolib.h"
 +#include "gpiolib-of.h"
 +#include "gpiolib-acpi.h"
  
  #define CREATE_TRACE_POINTS
  #include <trace/events/gpio.h>
@@@ -214,7 -213,7 +214,7 @@@ int gpiod_get_direction(struct gpio_des
  {
        struct gpio_chip *chip;
        unsigned offset;
 -      int status;
 +      int ret;
  
        chip = gpiod_to_chip(desc);
        offset = gpio_chip_hwgpio(desc);
@@@ -222,17 -221,17 +222,17 @@@
        if (!chip->get_direction)
                return -ENOTSUPP;
  
 -      status = chip->get_direction(chip, offset);
 -      if (status > 0) {
 +      ret = chip->get_direction(chip, offset);
 +      if (ret > 0) {
                /* GPIOF_DIR_IN, or other positive */
 -              status = 1;
 +              ret = 1;
                clear_bit(FLAG_IS_OUT, &desc->flags);
        }
 -      if (status == 0) {
 +      if (ret == 0) {
                /* GPIOF_DIR_OUT */
                set_bit(FLAG_IS_OUT, &desc->flags);
        }
 -      return status;
 +      return ret;
  }
  EXPORT_SYMBOL_GPL(gpiod_get_direction);
  
@@@ -351,7 -350,7 +351,7 @@@ static unsigned long *gpiochip_allocate
  {
        unsigned long *p;
  
 -      p = kmalloc_array(BITS_TO_LONGS(chip->ngpio), sizeof(*p), GFP_KERNEL);
 +      p = bitmap_alloc(chip->ngpio, GFP_KERNEL);
        if (!p)
                return NULL;
  
@@@ -361,31 -360,38 +361,31 @@@
        return p;
  }
  
 -static int gpiochip_alloc_valid_mask(struct gpio_chip *gpiochip)
 +static int gpiochip_alloc_valid_mask(struct gpio_chip *gc)
  {
 -#ifdef CONFIG_OF_GPIO
 -      int size;
 -      struct device_node *np = gpiochip->of_node;
 -
 -      size = of_property_count_u32_elems(np,  "gpio-reserved-ranges");
 -      if (size > 0 && size % 2 == 0)
 -              gpiochip->need_valid_mask = true;
 -#endif
 -
 -      if (!gpiochip->need_valid_mask)
 +      if (!(of_gpio_need_valid_mask(gc) || gc->init_valid_mask))
                return 0;
  
 -      gpiochip->valid_mask = gpiochip_allocate_mask(gpiochip);
 -      if (!gpiochip->valid_mask)
 +      gc->valid_mask = gpiochip_allocate_mask(gc);
 +      if (!gc->valid_mask)
                return -ENOMEM;
  
        return 0;
  }
  
 -static int gpiochip_init_valid_mask(struct gpio_chip *gpiochip)
 +static int gpiochip_init_valid_mask(struct gpio_chip *gc)
  {
 -      if (gpiochip->init_valid_mask)
 -              return gpiochip->init_valid_mask(gpiochip);
 +      if (gc->init_valid_mask)
 +              return gc->init_valid_mask(gc,
 +                                         gc->valid_mask,
 +                                         gc->ngpio);
  
        return 0;
  }
  
  static void gpiochip_free_valid_mask(struct gpio_chip *gpiochip)
  {
 -      kfree(gpiochip->valid_mask);
 +      bitmap_free(gpiochip->valid_mask);
        gpiochip->valid_mask = NULL;
  }
  
@@@ -529,14 -535,6 +529,14 @@@ static int linehandle_create(struct gpi
        if (lflags & ~GPIOHANDLE_REQUEST_VALID_FLAGS)
                return -EINVAL;
  
 +      /*
 +       * Do not allow both INPUT & OUTPUT flags to be set as they are
 +       * contradictory.
 +       */
 +      if ((lflags & GPIOHANDLE_REQUEST_INPUT) &&
 +          (lflags & GPIOHANDLE_REQUEST_OUTPUT))
 +              return -EINVAL;
 +
        /*
         * Do not allow OPEN_SOURCE & OPEN_DRAIN flags in a single request. If
         * the hardware actually supports enabling both at the same time the
@@@ -859,7 -857,7 +859,7 @@@ static irqreturn_t lineevent_irq_thread
        }
  
        ret = kfifo_put(&le->events, ge);
 -      if (ret != 0)
 +      if (ret)
                wake_up_poll(&le->wait, EPOLLIN);
  
        return IRQ_HANDLED;
@@@ -928,9 -926,7 +928,9 @@@ static int lineevent_create(struct gpio
        }
  
        /* This is just wrong: we don't look for events on output lines */
 -      if (lflags & GPIOHANDLE_REQUEST_OUTPUT) {
 +      if ((lflags & GPIOHANDLE_REQUEST_OUTPUT) ||
 +          (lflags & GPIOHANDLE_REQUEST_OPEN_DRAIN) ||
 +          (lflags & GPIOHANDLE_REQUEST_OPEN_SOURCE)) {
                ret = -EINVAL;
                goto out_free_label;
        }
@@@ -944,6 -940,10 +944,6 @@@
  
        if (lflags & GPIOHANDLE_REQUEST_ACTIVE_LOW)
                set_bit(FLAG_ACTIVE_LOW, &desc->flags);
 -      if (lflags & GPIOHANDLE_REQUEST_OPEN_DRAIN)
 -              set_bit(FLAG_OPEN_DRAIN, &desc->flags);
 -      if (lflags & GPIOHANDLE_REQUEST_OPEN_SOURCE)
 -              set_bit(FLAG_OPEN_SOURCE, &desc->flags);
  
        ret = gpiod_direction_input(desc);
        if (ret)
@@@ -1084,18 -1084,17 +1084,19 @@@ static long gpio_ioctl(struct file *fil
                    test_bit(FLAG_IS_HOGGED, &desc->flags) ||
                    test_bit(FLAG_USED_AS_IRQ, &desc->flags) ||
                    test_bit(FLAG_EXPORT, &desc->flags) ||
-                   test_bit(FLAG_SYSFS, &desc->flags))
+                   test_bit(FLAG_SYSFS, &desc->flags) ||
+                   !pinctrl_gpio_can_use_line(chip->base + lineinfo.line_offset))
                        lineinfo.flags |= GPIOLINE_FLAG_KERNEL;
                if (test_bit(FLAG_IS_OUT, &desc->flags))
                        lineinfo.flags |= GPIOLINE_FLAG_IS_OUT;
                if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
                        lineinfo.flags |= GPIOLINE_FLAG_ACTIVE_LOW;
                if (test_bit(FLAG_OPEN_DRAIN, &desc->flags))
 -                      lineinfo.flags |= GPIOLINE_FLAG_OPEN_DRAIN;
 +                      lineinfo.flags |= (GPIOLINE_FLAG_OPEN_DRAIN |
 +                                         GPIOLINE_FLAG_IS_OUT);
                if (test_bit(FLAG_OPEN_SOURCE, &desc->flags))
 -                      lineinfo.flags |= GPIOLINE_FLAG_OPEN_SOURCE;
 +                      lineinfo.flags |= (GPIOLINE_FLAG_OPEN_SOURCE |
 +                                         GPIOLINE_FLAG_IS_OUT);
  
                if (copy_to_user(ip, &lineinfo, sizeof(lineinfo)))
                        return -EFAULT;
@@@ -1176,21 -1175,21 +1177,21 @@@ static void gpiodevice_release(struct d
  
  static int gpiochip_setup_dev(struct gpio_device *gdev)
  {
 -      int status;
 +      int ret;
  
        cdev_init(&gdev->chrdev, &gpio_fileops);
        gdev->chrdev.owner = THIS_MODULE;
        gdev->dev.devt = MKDEV(MAJOR(gpio_devt), gdev->id);
  
 -      status = cdev_device_add(&gdev->chrdev, &gdev->dev);
 -      if (status)
 -              return status;
 +      ret = cdev_device_add(&gdev->chrdev, &gdev->dev);
 +      if (ret)
 +              return ret;
  
        chip_dbg(gdev->chip, "added GPIO chardev (%d:%d)\n",
                 MAJOR(gpio_devt), gdev->id);
  
 -      status = gpiochip_sysfs_register(gdev);
 -      if (status)
 +      ret = gpiochip_sysfs_register(gdev);
 +      if (ret)
                goto err_remove_device;
  
        /* From this point, the .release() function cleans up gpio_device */
@@@ -1203,7 -1202,7 +1204,7 @@@
  
  err_remove_device:
        cdev_device_del(&gdev->chrdev, &gdev->dev);
 -      return status;
 +      return ret;
  }
  
  static void gpiochip_machine_hog(struct gpio_chip *chip, struct gpiod_hog *hog)
@@@ -1244,13 -1243,13 +1245,13 @@@ static void machine_gpiochip_add(struc
  static void gpiochip_setup_devs(void)
  {
        struct gpio_device *gdev;
 -      int err;
 +      int ret;
  
        list_for_each_entry(gdev, &gpio_devices, list) {
 -              err = gpiochip_setup_dev(gdev);
 -              if (err)
 +              ret = gpiochip_setup_dev(gdev);
 +              if (ret)
                        pr_err("%s: Failed to initialize gpio device (%d)\n",
 -                             dev_name(&gdev->dev), err);
 +                             dev_name(&gdev->dev), ret);
        }
  }
  
@@@ -1259,7 -1258,7 +1260,7 @@@ int gpiochip_add_data_with_key(struct g
                               struct lock_class_key *request_key)
  {
        unsigned long   flags;
 -      int             status = 0;
 +      int             ret = 0;
        unsigned        i;
        int             base = chip->base;
        struct gpio_device *gdev;
@@@ -1289,7 -1288,7 +1290,7 @@@
  
        gdev->id = ida_simple_get(&gpio_ida, 0, 0, GFP_KERNEL);
        if (gdev->id < 0) {
 -              status = gdev->id;
 +              ret = gdev->id;
                goto err_free_gdev;
        }
        dev_set_name(&gdev->dev, "gpiochip%d", gdev->id);
@@@ -1305,13 -1304,13 +1306,13 @@@
  
        gdev->descs = kcalloc(chip->ngpio, sizeof(gdev->descs[0]), GFP_KERNEL);
        if (!gdev->descs) {
 -              status = -ENOMEM;
 +              ret = -ENOMEM;
                goto err_free_ida;
        }
  
        if (chip->ngpio == 0) {
                chip_err(chip, "tried to insert a GPIO chip with zero lines\n");
 -              status = -EINVAL;
 +              ret = -EINVAL;
                goto err_free_descs;
        }
  
@@@ -1321,7 -1320,7 +1322,7 @@@
  
        gdev->label = kstrdup_const(chip->label ?: "unknown", GFP_KERNEL);
        if (!gdev->label) {
 -              status = -ENOMEM;
 +              ret = -ENOMEM;
                goto err_free_descs;
        }
  
@@@ -1340,7 -1339,7 +1341,7 @@@
        if (base < 0) {
                base = gpiochip_find_base(chip->ngpio);
                if (base < 0) {
 -                      status = base;
 +                      ret = base;
                        spin_unlock_irqrestore(&gpio_lock, flags);
                        goto err_free_label;
                }
@@@ -1354,8 -1353,8 +1355,8 @@@
        }
        gdev->base = base;
  
 -      status = gpiodev_add_to_list(gdev);
 -      if (status) {
 +      ret = gpiodev_add_to_list(gdev);
 +      if (ret) {
                spin_unlock_irqrestore(&gpio_lock, flags);
                goto err_free_label;
        }
@@@ -1369,20 -1368,28 +1370,20 @@@
        INIT_LIST_HEAD(&gdev->pin_ranges);
  #endif
  
 -      status = gpiochip_set_desc_names(chip);
 -      if (status)
 +      ret = gpiochip_set_desc_names(chip);
 +      if (ret)
                goto err_remove_from_list;
  
 -      status = gpiochip_irqchip_init_valid_mask(chip);
 -      if (status)
 +      ret = gpiochip_alloc_valid_mask(chip);
 +      if (ret)
                goto err_remove_from_list;
  
 -      status = gpiochip_alloc_valid_mask(chip);
 -      if (status)
 -              goto err_remove_irqchip_mask;
 -
 -      status = gpiochip_add_irqchip(chip, lock_key, request_key);
 -      if (status)
 +      ret = of_gpiochip_add(chip);
 +      if (ret)
                goto err_free_gpiochip_mask;
  
 -      status = of_gpiochip_add(chip);
 -      if (status)
 -              goto err_remove_chip;
 -
 -      status = gpiochip_init_valid_mask(chip);
 -      if (status)
 +      ret = gpiochip_init_valid_mask(chip);
 +      if (ret)
                goto err_remove_of_chip;
  
        for (i = 0; i < chip->ngpio; i++) {
@@@ -1405,14 -1412,6 +1406,14 @@@
  
        machine_gpiochip_add(chip);
  
 +      ret = gpiochip_irqchip_init_valid_mask(chip);
 +      if (ret)
 +              goto err_remove_acpi_chip;
 +
 +      ret = gpiochip_add_irqchip(chip, lock_key, request_key);
 +      if (ret)
 +              goto err_remove_irqchip_mask;
 +
        /*
         * By first adding the chardev, and then adding the device,
         * we get a device node entry in sysfs under
@@@ -1422,23 -1421,23 +1423,23 @@@
         * Otherwise, defer until later.
         */
        if (gpiolib_initialized) {
 -              status = gpiochip_setup_dev(gdev);
 -              if (status)
 -                      goto err_remove_acpi_chip;
 +              ret = gpiochip_setup_dev(gdev);
 +              if (ret)
 +                      goto err_remove_irqchip;
        }
        return 0;
  
 +err_remove_irqchip:
 +      gpiochip_irqchip_remove(chip);
 +err_remove_irqchip_mask:
 +      gpiochip_irqchip_free_valid_mask(chip);
  err_remove_acpi_chip:
        acpi_gpiochip_remove(chip);
  err_remove_of_chip:
        gpiochip_free_hogs(chip);
        of_gpiochip_remove(chip);
 -err_remove_chip:
 -      gpiochip_irqchip_remove(chip);
  err_free_gpiochip_mask:
        gpiochip_free_valid_mask(chip);
 -err_remove_irqchip_mask:
 -      gpiochip_irqchip_free_valid_mask(chip);
  err_remove_from_list:
        spin_lock_irqsave(&gpio_lock, flags);
        list_del(&gdev->list);
@@@ -1453,9 -1452,9 +1454,9 @@@ err_free_gdev
        /* failures here can mean systems won't boot... */
        pr_err("%s: GPIOs %d..%d (%s) failed to register, %d\n", __func__,
               gdev->base, gdev->base + gdev->ngpio - 1,
 -             chip->label ? : "generic", status);
 +             chip->label ? : "generic", ret);
        kfree(gdev);
 -      return status;
 +      return ret;
  }
  EXPORT_SYMBOL_GPL(gpiochip_add_data_with_key);
  
@@@ -1621,25 -1620,21 +1622,25 @@@ static struct gpio_chip *find_chip_by_n
   * The following is irqchip helper code for gpiochips.
   */
  
 -static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip)
 +static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gc)
  {
 -      if (!gpiochip->irq.need_valid_mask)
 +      struct gpio_irq_chip *girq = &gc->irq;
 +
 +      if (!girq->init_valid_mask)
                return 0;
  
 -      gpiochip->irq.valid_mask = gpiochip_allocate_mask(gpiochip);
 -      if (!gpiochip->irq.valid_mask)
 +      girq->valid_mask = gpiochip_allocate_mask(gc);
 +      if (!girq->valid_mask)
                return -ENOMEM;
  
 +      girq->init_valid_mask(gc, girq->valid_mask, gc->ngpio);
 +
        return 0;
  }
  
  static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip)
  {
 -      kfree(gpiochip->irq.valid_mask);
 +      bitmap_free(gpiochip->irq.valid_mask);
        gpiochip->irq.valid_mask = NULL;
  }
  
@@@ -1739,273 -1734,6 +1740,273 @@@ void gpiochip_set_nested_irqchip(struc
  }
  EXPORT_SYMBOL_GPL(gpiochip_set_nested_irqchip);
  
 +#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
 +
 +/**
 + * gpiochip_set_hierarchical_irqchip() - connects a hierarchical irqchip
 + * to a gpiochip
 + * @gc: the gpiochip to set the irqchip hierarchical handler to
 + * @irqchip: the irqchip to handle this level of the hierarchy, the interrupt
 + * will then percolate up to the parent
 + */
 +static void gpiochip_set_hierarchical_irqchip(struct gpio_chip *gc,
 +                                            struct irq_chip *irqchip)
 +{
 +      /* DT will deal with mapping each IRQ as we go along */
 +      if (is_of_node(gc->irq.fwnode))
 +              return;
 +
 +      /*
 +       * This is for legacy and boardfile "irqchip" fwnodes: allocate
 +       * irqs upfront instead of dynamically since we don't have the
 +       * dynamic type of allocation that hardware description languages
 +       * provide. Once all GPIO drivers using board files are gone from
 +       * the kernel we can delete this code, but for a transitional period
 +       * it is necessary to keep this around.
 +       */
 +      if (is_fwnode_irqchip(gc->irq.fwnode)) {
 +              int i;
 +              int ret;
 +
 +              for (i = 0; i < gc->ngpio; i++) {
 +                      struct irq_fwspec fwspec;
 +                      unsigned int parent_hwirq;
 +                      unsigned int parent_type;
 +                      struct gpio_irq_chip *girq = &gc->irq;
 +
 +                      /*
 +                       * We call the child to parent translation function
 +                       * only to check if the child IRQ is valid or not.
 +                       * Just pick the rising edge type here as that is what
 +                       * we likely need to support.
 +                       */
 +                      ret = girq->child_to_parent_hwirq(gc, i,
 +                                                        IRQ_TYPE_EDGE_RISING,
 +                                                        &parent_hwirq,
 +                                                        &parent_type);
 +                      if (ret) {
 +                              chip_err(gc, "skip set-up on hwirq %d\n",
 +                                       i);
 +                              continue;
 +                      }
 +
 +                      fwspec.fwnode = gc->irq.fwnode;
 +                      /* This is the hwirq for the GPIO line side of things */
 +                      fwspec.param[0] = girq->child_offset_to_irq(gc, i);
 +                      /* Just pick something */
 +                      fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
 +                      fwspec.param_count = 2;
 +                      ret = __irq_domain_alloc_irqs(gc->irq.domain,
 +                                                    /* just pick something */
 +                                                    -1,
 +                                                    1,
 +                                                    NUMA_NO_NODE,
 +                                                    &fwspec,
 +                                                    false,
 +                                                    NULL);
 +                      if (ret < 0) {
 +                              chip_err(gc,
 +                                       "can not allocate irq for GPIO line %d parent hwirq %d in hierarchy domain: %d\n",
 +                                       i, parent_hwirq,
 +                                       ret);
 +                      }
 +              }
 +      }
 +
 +      chip_err(gc, "%s unknown fwnode type proceed anyway\n", __func__);
 +
 +      return;
 +}
 +
 +static int gpiochip_hierarchy_irq_domain_translate(struct irq_domain *d,
 +                                                 struct irq_fwspec *fwspec,
 +                                                 unsigned long *hwirq,
 +                                                 unsigned int *type)
 +{
 +      /* We support standard DT translation */
 +      if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
 +              return irq_domain_translate_twocell(d, fwspec, hwirq, type);
 +      }
 +
 +      /* This is for board files and others not using DT */
 +      if (is_fwnode_irqchip(fwspec->fwnode)) {
 +              int ret;
 +
 +              ret = irq_domain_translate_twocell(d, fwspec, hwirq, type);
 +              if (ret)
 +                      return ret;
 +              WARN_ON(*type == IRQ_TYPE_NONE);
 +              return 0;
 +      }
 +      return -EINVAL;
 +}
 +
 +static int gpiochip_hierarchy_irq_domain_alloc(struct irq_domain *d,
 +                                             unsigned int irq,
 +                                             unsigned int nr_irqs,
 +                                             void *data)
 +{
 +      struct gpio_chip *gc = d->host_data;
 +      irq_hw_number_t hwirq;
 +      unsigned int type = IRQ_TYPE_NONE;
 +      struct irq_fwspec *fwspec = data;
 +      struct irq_fwspec parent_fwspec;
 +      unsigned int parent_hwirq;
 +      unsigned int parent_type;
 +      struct gpio_irq_chip *girq = &gc->irq;
 +      int ret;
 +
 +      /*
 +       * The nr_irqs parameter is always one except for PCI multi-MSI
 +       * so this should not happen.
 +       */
 +      WARN_ON(nr_irqs != 1);
 +
 +      ret = gc->irq.child_irq_domain_ops.translate(d, fwspec, &hwirq, &type);
 +      if (ret)
 +              return ret;
 +
 +      chip_info(gc, "allocate IRQ %d, hwirq %lu\n", irq,  hwirq);
 +
 +      ret = girq->child_to_parent_hwirq(gc, hwirq, type,
 +                                        &parent_hwirq, &parent_type);
 +      if (ret) {
 +              chip_err(gc, "can't look up hwirq %lu\n", hwirq);
 +              return ret;
 +      }
 +      chip_info(gc, "found parent hwirq %u\n", parent_hwirq);
 +
 +      /*
 +       * We set handle_bad_irq because the .set_type() should
 +       * always be invoked and set the right type of handler.
 +       */
 +      irq_domain_set_info(d,
 +                          irq,
 +                          hwirq,
 +                          gc->irq.chip,
 +                          gc,
 +                          girq->handler,
 +                          NULL, NULL);
 +      irq_set_probe(irq);
 +
 +      /*
 +       * Create a IRQ fwspec to send up to the parent irqdomain:
 +       * specify the hwirq we address on the parent and tie it
 +       * all together up the chain.
 +       */
 +      parent_fwspec.fwnode = d->parent->fwnode;
 +      /* This parent only handles asserted level IRQs */
 +      girq->populate_parent_fwspec(gc, &parent_fwspec, parent_hwirq,
 +                                   parent_type);
 +      chip_info(gc, "alloc_irqs_parent for %d parent hwirq %d\n",
 +                irq, parent_hwirq);
 +      ret = irq_domain_alloc_irqs_parent(d, irq, 1, &parent_fwspec);
 +      if (ret)
 +              chip_err(gc,
 +                       "failed to allocate parent hwirq %d for hwirq %lu\n",
 +                       parent_hwirq, hwirq);
 +
 +      return ret;
 +}
 +
 +static unsigned int gpiochip_child_offset_to_irq_noop(struct gpio_chip *chip,
 +                                                    unsigned int offset)
 +{
 +      return offset;
 +}
 +
 +static void gpiochip_hierarchy_setup_domain_ops(struct irq_domain_ops *ops)
 +{
 +      ops->activate = gpiochip_irq_domain_activate;
 +      ops->deactivate = gpiochip_irq_domain_deactivate;
 +      ops->alloc = gpiochip_hierarchy_irq_domain_alloc;
 +      ops->free = irq_domain_free_irqs_common;
 +
 +      /*
 +       * We only allow overriding the translate() function for
 +       * hierarchical chips, and this should only be done if the user
 +       * really need something other than 1:1 translation.
 +       */
 +      if (!ops->translate)
 +              ops->translate = gpiochip_hierarchy_irq_domain_translate;
 +}
 +
 +static int gpiochip_hierarchy_add_domain(struct gpio_chip *gc)
 +{
 +      if (!gc->irq.child_to_parent_hwirq ||
 +          !gc->irq.fwnode) {
 +              chip_err(gc, "missing irqdomain vital data\n");
 +              return -EINVAL;
 +      }
 +
 +      if (!gc->irq.child_offset_to_irq)
 +              gc->irq.child_offset_to_irq = gpiochip_child_offset_to_irq_noop;
 +
 +      if (!gc->irq.populate_parent_fwspec)
 +              gc->irq.populate_parent_fwspec =
 +                      gpiochip_populate_parent_fwspec_twocell;
 +
 +      gpiochip_hierarchy_setup_domain_ops(&gc->irq.child_irq_domain_ops);
 +
 +      gc->irq.domain = irq_domain_create_hierarchy(
 +              gc->irq.parent_domain,
 +              0,
 +              gc->ngpio,
 +              gc->irq.fwnode,
 +              &gc->irq.child_irq_domain_ops,
 +              gc);
 +
 +      if (!gc->irq.domain)
 +              return -ENOMEM;
 +
 +      gpiochip_set_hierarchical_irqchip(gc, gc->irq.chip);
 +
 +      return 0;
 +}
 +
 +static bool gpiochip_hierarchy_is_hierarchical(struct gpio_chip *gc)
 +{
 +      return !!gc->irq.parent_domain;
 +}
 +
 +void gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *chip,
 +                                           struct irq_fwspec *fwspec,
 +                                           unsigned int parent_hwirq,
 +                                           unsigned int parent_type)
 +{
 +      fwspec->param_count = 2;
 +      fwspec->param[0] = parent_hwirq;
 +      fwspec->param[1] = parent_type;
 +}
 +EXPORT_SYMBOL_GPL(gpiochip_populate_parent_fwspec_twocell);
 +
 +void gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *chip,
 +                                            struct irq_fwspec *fwspec,
 +                                            unsigned int parent_hwirq,
 +                                            unsigned int parent_type)
 +{
 +      fwspec->param_count = 4;
 +      fwspec->param[0] = 0;
 +      fwspec->param[1] = parent_hwirq;
 +      fwspec->param[2] = 0;
 +      fwspec->param[3] = parent_type;
 +}
 +EXPORT_SYMBOL_GPL(gpiochip_populate_parent_fwspec_fourcell);
 +
 +#else
 +
 +static int gpiochip_hierarchy_add_domain(struct gpio_chip *gc)
 +{
 +      return -EINVAL;
 +}
 +
 +static bool gpiochip_hierarchy_is_hierarchical(struct gpio_chip *gc)
 +{
 +      return false;
 +}
 +
 +#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
 +
  /**
   * gpiochip_irq_map() - maps an IRQ into a GPIO irqchip
   * @d: the irqdomain used by this irqchip
@@@ -2020,7 -1748,7 +2021,7 @@@ int gpiochip_irq_map(struct irq_domain 
                     irq_hw_number_t hwirq)
  {
        struct gpio_chip *chip = d->host_data;
 -      int err = 0;
 +      int ret = 0;
  
        if (!gpiochip_irqchip_irq_valid(chip, hwirq))
                return -ENXIO;
@@@ -2038,12 -1766,12 +2039,12 @@@
        irq_set_noprobe(irq);
  
        if (chip->irq.num_parents == 1)
 -              err = irq_set_parent(irq, chip->irq.parents[0]);
 +              ret = irq_set_parent(irq, chip->irq.parents[0]);
        else if (chip->irq.map)
 -              err = irq_set_parent(irq, chip->irq.map[hwirq]);
 +              ret = irq_set_parent(irq, chip->irq.map[hwirq]);
  
 -      if (err < 0)
 -              return err;
 +      if (ret < 0)
 +              return ret;
  
        /*
         * No set-up of the hardware will happen if IRQ_TYPE_NONE
@@@ -2074,11 -1802,6 +2075,11 @@@ static const struct irq_domain_ops gpio
        .xlate  = irq_domain_xlate_twocell,
  };
  
 +/*
 + * TODO: move these activate/deactivate in under the hierarchicial
 + * irqchip implementation as static once SPMI and SSBI (all external
 + * users) are phased over.
 + */
  /**
   * gpiochip_irq_domain_activate() - Lock a GPIO to be used as an IRQ
   * @domain: The IRQ domain used by this IRQ chip
@@@ -2118,25 -1841,10 +2119,25 @@@ EXPORT_SYMBOL_GPL(gpiochip_irq_domain_d
  
  static int gpiochip_to_irq(struct gpio_chip *chip, unsigned offset)
  {
 +      struct irq_domain *domain = chip->irq.domain;
 +
        if (!gpiochip_irqchip_irq_valid(chip, offset))
                return -ENXIO;
  
 -      return irq_create_mapping(chip->irq.domain, offset);
 +#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
 +      if (irq_domain_is_hierarchy(domain)) {
 +              struct irq_fwspec spec;
 +
 +              spec.fwnode = domain->fwnode;
 +              spec.param_count = 2;
 +              spec.param[0] = chip->irq.child_offset_to_irq(chip, offset);
 +              spec.param[1] = IRQ_TYPE_NONE;
 +
 +              return irq_create_fwspec_mapping(&spec);
 +      }
 +#endif
 +
 +      return irq_create_mapping(domain, offset);
  }
  
  static int gpiochip_irq_reqres(struct irq_data *d)
@@@ -2213,7 -1921,7 +2214,7 @@@ static int gpiochip_add_irqchip(struct 
                                struct lock_class_key *request_key)
  {
        struct irq_chip *irqchip = gpiochip->irq.chip;
 -      const struct irq_domain_ops *ops;
 +      const struct irq_domain_ops *ops = NULL;
        struct device_node *np;
        unsigned int type;
        unsigned int i;
@@@ -2249,25 -1957,16 +2250,25 @@@
        gpiochip->irq.lock_key = lock_key;
        gpiochip->irq.request_key = request_key;
  
 -      if (gpiochip->irq.domain_ops)
 -              ops = gpiochip->irq.domain_ops;
 -      else
 -              ops = &gpiochip_domain_ops;
 -
 -      gpiochip->irq.domain = irq_domain_add_simple(np, gpiochip->ngpio,
 -                                                   gpiochip->irq.first,
 -                                                   ops, gpiochip);
 -      if (!gpiochip->irq.domain)
 -              return -EINVAL;
 +      /* If a parent irqdomain is provided, let's build a hierarchy */
 +      if (gpiochip_hierarchy_is_hierarchical(gpiochip)) {
 +              int ret = gpiochip_hierarchy_add_domain(gpiochip);
 +              if (ret)
 +                      return ret;
 +      } else {
 +              /* Some drivers provide custom irqdomain ops */
 +              if (gpiochip->irq.domain_ops)
 +                      ops = gpiochip->irq.domain_ops;
 +
 +              if (!ops)
 +                      ops = &gpiochip_domain_ops;
 +              gpiochip->irq.domain = irq_domain_add_simple(np,
 +                      gpiochip->ngpio,
 +                      gpiochip->irq.first,
 +                      ops, gpiochip);
 +              if (!gpiochip->irq.domain)
 +                      return -EINVAL;
 +      }
  
        if (gpiochip->irq.parent_handler) {
                void *data = gpiochip->irq.parent_handler_data ?: gpiochip;
@@@ -2630,7 -2329,7 +2631,7 @@@ EXPORT_SYMBOL_GPL(gpiochip_remove_pin_r
  static int gpiod_request_commit(struct gpio_desc *desc, const char *label)
  {
        struct gpio_chip        *chip = desc->gdev->chip;
 -      int                     status;
 +      int                     ret;
        unsigned long           flags;
        unsigned                offset;
  
@@@ -2648,10 -2347,10 +2649,10 @@@
  
        if (test_and_set_bit(FLAG_REQUESTED, &desc->flags) == 0) {
                desc_set_label(desc, label ? : "?");
 -              status = 0;
 +              ret = 0;
        } else {
                kfree_const(label);
 -              status = -EBUSY;
 +              ret = -EBUSY;
                goto done;
        }
  
@@@ -2660,12 -2359,12 +2661,12 @@@
                spin_unlock_irqrestore(&gpio_lock, flags);
                offset = gpio_chip_hwgpio(desc);
                if (gpiochip_line_is_valid(chip, offset))
 -                      status = chip->request(chip, offset);
 +                      ret = chip->request(chip, offset);
                else
 -                      status = -EINVAL;
 +                      ret = -EINVAL;
                spin_lock_irqsave(&gpio_lock, flags);
  
 -              if (status < 0) {
 +              if (ret < 0) {
                        desc_set_label(desc, NULL);
                        kfree_const(label);
                        clear_bit(FLAG_REQUESTED, &desc->flags);
@@@ -2680,7 -2379,7 +2681,7 @@@
        }
  done:
        spin_unlock_irqrestore(&gpio_lock, flags);
 -      return status;
 +      return ret;
  }
  
  /*
@@@ -2723,24 -2422,24 +2724,24 @@@ static int validate_desc(const struct g
  
  int gpiod_request(struct gpio_desc *desc, const char *label)
  {
 -      int status = -EPROBE_DEFER;
 +      int ret = -EPROBE_DEFER;
        struct gpio_device *gdev;
  
        VALIDATE_DESC(desc);
        gdev = desc->gdev;
  
        if (try_module_get(gdev->owner)) {
 -              status = gpiod_request_commit(desc, label);
 -              if (status < 0)
 +              ret = gpiod_request_commit(desc, label);
 +              if (ret < 0)
                        module_put(gdev->owner);
                else
                        get_device(&gdev->dev);
        }
  
 -      if (status)
 -              gpiod_dbg(desc, "%s: status %d\n", __func__, status);
 +      if (ret)
 +              gpiod_dbg(desc, "%s: status %d\n", __func__, ret);
  
 -      return status;
 +      return ret;
  }
  
  static bool gpiod_free_commit(struct gpio_desc *desc)
@@@ -2842,22 -2541,22 +2843,22 @@@ struct gpio_desc *gpiochip_request_own_
                                            enum gpiod_flags dflags)
  {
        struct gpio_desc *desc = gpiochip_get_desc(chip, hwnum);
 -      int err;
 +      int ret;
  
        if (IS_ERR(desc)) {
                chip_err(chip, "failed to get GPIO descriptor\n");
                return desc;
        }
  
 -      err = gpiod_request_commit(desc, label);
 -      if (err < 0)
 -              return ERR_PTR(err);
 +      ret = gpiod_request_commit(desc, label);
 +      if (ret < 0)
 +              return ERR_PTR(ret);
  
 -      err = gpiod_configure_flags(desc, label, lflags, dflags);
 -      if (err) {
 +      ret = gpiod_configure_flags(desc, label, lflags, dflags);
 +      if (ret) {
                chip_err(chip, "setup of own GPIO %s failed\n", label);
                gpiod_free_commit(desc);
 -              return ERR_PTR(err);
 +              return ERR_PTR(ret);
        }
  
        return desc;
@@@ -2920,7 -2619,7 +2921,7 @@@ static int gpio_set_config(struct gpio_
  int gpiod_direction_input(struct gpio_desc *desc)
  {
        struct gpio_chip        *chip;
 -      int                     status = 0;
 +      int                     ret = 0;
  
        VALIDATE_DESC(desc);
        chip = desc->gdev->chip;
@@@ -2944,7 -2643,7 +2945,7 @@@
         * assume we are in input mode after this.
         */
        if (chip->direction_input) {
 -              status = chip->direction_input(chip, gpio_chip_hwgpio(desc));
 +              ret = chip->direction_input(chip, gpio_chip_hwgpio(desc));
        } else if (chip->get_direction &&
                  (chip->get_direction(chip, gpio_chip_hwgpio(desc)) != 1)) {
                gpiod_warn(desc,
@@@ -2952,7 -2651,7 +2953,7 @@@
                           __func__);
                return -EIO;
        }
 -      if (status == 0)
 +      if (ret == 0)
                clear_bit(FLAG_IS_OUT, &desc->flags);
  
        if (test_bit(FLAG_PULL_UP, &desc->flags))
@@@ -2962,9 -2661,9 +2963,9 @@@
                gpio_set_config(chip, gpio_chip_hwgpio(desc),
                                PIN_CONFIG_BIAS_PULL_DOWN);
  
 -      trace_gpio_direction(desc_to_gpio(desc), 1, status);
 +      trace_gpio_direction(desc_to_gpio(desc), 1, ret);
  
 -      return status;
 +      return ret;
  }
  EXPORT_SYMBOL_GPL(gpiod_direction_input);
  
@@@ -3236,7 -2935,7 +3237,7 @@@ int gpiod_get_array_value_complex(bool 
                                  struct gpio_array *array_info,
                                  unsigned long *value_bitmap)
  {
 -      int err, i = 0;
 +      int ret, i = 0;
  
        /*
         * Validate array_info against desc_array and its size.
@@@ -3249,11 -2948,11 +3250,11 @@@
                if (!can_sleep)
                        WARN_ON(array_info->chip->can_sleep);
  
 -              err = gpio_chip_get_multiple(array_info->chip,
 +              ret = gpio_chip_get_multiple(array_info->chip,
                                             array_info->get_mask,
                                             value_bitmap);
 -              if (err)
 -                      return err;
 +              if (ret)
 +                      return ret;
  
                if (!raw && !bitmap_empty(array_info->invert_mask, array_size))
                        bitmap_xor(value_bitmap, value_bitmap,
@@@ -3441,24 -3140,24 +3442,24 @@@ EXPORT_SYMBOL_GPL(gpiod_get_array_value
   */
  static void gpio_set_open_drain_value_commit(struct gpio_desc *desc, bool value)
  {
 -      int err = 0;
 +      int ret = 0;
        struct gpio_chip *chip = desc->gdev->chip;
        int offset = gpio_chip_hwgpio(desc);
  
        if (value) {
 -              err = chip->direction_input(chip, offset);
 -              if (!err)
 +              ret = chip->direction_input(chip, offset);
 +              if (!ret)
                        clear_bit(FLAG_IS_OUT, &desc->flags);
        } else {
 -              err = chip->direction_output(chip, offset, 0);
 -              if (!err)
 +              ret = chip->direction_output(chip, offset, 0);
 +              if (!ret)
                        set_bit(FLAG_IS_OUT, &desc->flags);
        }
 -      trace_gpio_direction(desc_to_gpio(desc), value, err);
 -      if (err < 0)
 +      trace_gpio_direction(desc_to_gpio(desc), value, ret);
 +      if (ret < 0)
                gpiod_err(desc,
                          "%s: Error in set_value for open drain err %d\n",
 -                        __func__, err);
 +                        __func__, ret);
  }
  
  /*
@@@ -3468,24 -3167,24 +3469,24 @@@
   */
  static void gpio_set_open_source_value_commit(struct gpio_desc *desc, bool value)
  {
 -      int err = 0;
 +      int ret = 0;
        struct gpio_chip *chip = desc->gdev->chip;
        int offset = gpio_chip_hwgpio(desc);
  
        if (value) {
 -              err = chip->direction_output(chip, offset, 1);
 -              if (!err)
 +              ret = chip->direction_output(chip, offset, 1);
 +              if (!ret)
                        set_bit(FLAG_IS_OUT, &desc->flags);
        } else {
 -              err = chip->direction_input(chip, offset);
 -              if (!err)
 +              ret = chip->direction_input(chip, offset);
 +              if (!ret)
                        clear_bit(FLAG_IS_OUT, &desc->flags);
        }
 -      trace_gpio_direction(desc_to_gpio(desc), !value, err);
 -      if (err < 0)
 +      trace_gpio_direction(desc_to_gpio(desc), !value, ret);
 +      if (ret < 0)
                gpiod_err(desc,
                          "%s: Error in set_value for open source err %d\n",
 -                        __func__, err);
 +                        __func__, ret);
  }
  
  static void gpiod_set_raw_value_commit(struct gpio_desc *desc, bool value)
@@@ -4302,6 -4001,27 +4303,6 @@@ static struct gpio_desc *gpiod_find(str
        return desc;
  }
  
 -static int dt_gpio_count(struct device *dev, const char *con_id)
 -{
 -      int ret;
 -      char propname[32];
 -      unsigned int i;
 -
 -      for (i = 0; i < ARRAY_SIZE(gpio_suffixes); i++) {
 -              if (con_id)
 -                      snprintf(propname, sizeof(propname), "%s-%s",
 -                               con_id, gpio_suffixes[i]);
 -              else
 -                      snprintf(propname, sizeof(propname), "%s",
 -                               gpio_suffixes[i]);
 -
 -              ret = of_gpio_named_count(dev->of_node, propname);
 -              if (ret > 0)
 -                      break;
 -      }
 -      return ret ? ret : -ENOENT;
 -}
 -
  static int platform_gpio_count(struct device *dev, const char *con_id)
  {
        struct gpiod_lookup_table *table;
@@@ -4334,7 -4054,7 +4335,7 @@@ int gpiod_count(struct device *dev, con
        int count = -ENOENT;
  
        if (IS_ENABLED(CONFIG_OF) && dev && dev->of_node)
 -              count = dt_gpio_count(dev, con_id);
 +              count = of_gpio_get_count(dev, con_id);
        else if (IS_ENABLED(CONFIG_ACPI) && dev && ACPI_HANDLE(dev))
                count = acpi_gpio_count(dev, con_id);
  
@@@ -4396,7 -4116,7 +4397,7 @@@ EXPORT_SYMBOL_GPL(gpiod_get_optional)
  int gpiod_configure_flags(struct gpio_desc *desc, const char *con_id,
                unsigned long lflags, enum gpiod_flags dflags)
  {
 -      int status;
 +      int ret;
  
        if (lflags & GPIO_ACTIVE_LOW)
                set_bit(FLAG_ACTIVE_LOW, &desc->flags);
@@@ -4429,9 -4149,9 +4430,9 @@@
        else if (lflags & GPIO_PULL_DOWN)
                set_bit(FLAG_PULL_DOWN, &desc->flags);
  
 -      status = gpiod_set_transitory(desc, (lflags & GPIO_TRANSITORY));
 -      if (status < 0)
 -              return status;
 +      ret = gpiod_set_transitory(desc, (lflags & GPIO_TRANSITORY));
 +      if (ret < 0)
 +              return ret;
  
        /* No particular flag request, return here... */
        if (!(dflags & GPIOD_FLAGS_BIT_DIR_SET)) {
@@@ -4441,12 -4161,12 +4442,12 @@@
  
        /* Process flags */
        if (dflags & GPIOD_FLAGS_BIT_DIR_OUT)
 -              status = gpiod_direction_output(desc,
 +              ret = gpiod_direction_output(desc,
                                !!(dflags & GPIOD_FLAGS_BIT_DIR_VAL));
        else
 -              status = gpiod_direction_input(desc);
 +              ret = gpiod_direction_input(desc);
  
 -      return status;
 +      return ret;
  }
  
  /**
@@@ -4470,7 -4190,7 +4471,7 @@@ struct gpio_desc *__must_check gpiod_ge
  {
        unsigned long lookupflags = GPIO_LOOKUP_FLAGS_DEFAULT;
        struct gpio_desc *desc = NULL;
 -      int status;
 +      int ret;
        /* Maybe we have a device name, maybe not */
        const char *devname = dev ? dev_name(dev) : "?";
  
@@@ -4505,9 -4225,9 +4506,9 @@@
         * If a connection label was passed use that, else attempt to use
         * the device name as label
         */
 -      status = gpiod_request(desc, con_id ? con_id : devname);
 -      if (status < 0) {
 -              if (status == -EBUSY && flags & GPIOD_FLAGS_BIT_NONEXCLUSIVE) {
 +      ret = gpiod_request(desc, con_id ? con_id : devname);
 +      if (ret < 0) {
 +              if (ret == -EBUSY && flags & GPIOD_FLAGS_BIT_NONEXCLUSIVE) {
                        /*
                         * This happens when there are several consumers for
                         * the same GPIO line: we just return here without
@@@ -4520,20 -4240,89 +4521,20 @@@
                                 con_id ? con_id : devname);
                        return desc;
                } else {
 -                      return ERR_PTR(status);
 +                      return ERR_PTR(ret);
                }
        }
  
 -      status = gpiod_configure_flags(desc, con_id, lookupflags, flags);
 -      if (status < 0) {
 -              dev_dbg(dev, "setup of GPIO %s failed\n", con_id);
 -              gpiod_put(desc);
 -              return ERR_PTR(status);
 -      }
 -
 -      return desc;
 -}
 -EXPORT_SYMBOL_GPL(gpiod_get_index);
 -
 -/**
 - * gpiod_get_from_of_node() - obtain a GPIO from an OF node
 - * @node:     handle of the OF node
 - * @propname: name of the DT property representing the GPIO
 - * @index:    index of the GPIO to obtain for the consumer
 - * @dflags:   GPIO initialization flags
 - * @label:    label to attach to the requested GPIO
 - *
 - * Returns:
 - * On successful request the GPIO pin is configured in accordance with
 - * provided @dflags.
 - *
 - * In case of error an ERR_PTR() is returned.
 - */
 -struct gpio_desc *gpiod_get_from_of_node(struct device_node *node,
 -                                       const char *propname, int index,
 -                                       enum gpiod_flags dflags,
 -                                       const char *label)
 -{
 -      unsigned long lflags = GPIO_LOOKUP_FLAGS_DEFAULT;
 -      struct gpio_desc *desc;
 -      enum of_gpio_flags flags;
 -      bool active_low = false;
 -      bool single_ended = false;
 -      bool open_drain = false;
 -      bool transitory = false;
 -      int ret;
 -
 -      desc = of_get_named_gpiod_flags(node, propname,
 -                                      index, &flags);
 -
 -      if (!desc || IS_ERR(desc)) {
 -              return desc;
 -      }
 -
 -      active_low = flags & OF_GPIO_ACTIVE_LOW;
 -      single_ended = flags & OF_GPIO_SINGLE_ENDED;
 -      open_drain = flags & OF_GPIO_OPEN_DRAIN;
 -      transitory = flags & OF_GPIO_TRANSITORY;
 -
 -      ret = gpiod_request(desc, label);
 -      if (ret == -EBUSY && (flags & GPIOD_FLAGS_BIT_NONEXCLUSIVE))
 -              return desc;
 -      if (ret)
 -              return ERR_PTR(ret);
 -
 -      if (active_low)
 -              lflags |= GPIO_ACTIVE_LOW;
 -
 -      if (single_ended) {
 -              if (open_drain)
 -                      lflags |= GPIO_OPEN_DRAIN;
 -              else
 -                      lflags |= GPIO_OPEN_SOURCE;
 -      }
 -
 -      if (transitory)
 -              lflags |= GPIO_TRANSITORY;
 -
 -      ret = gpiod_configure_flags(desc, propname, lflags, dflags);
 +      ret = gpiod_configure_flags(desc, con_id, lookupflags, flags);
        if (ret < 0) {
 +              dev_dbg(dev, "setup of GPIO %s failed\n", con_id);
                gpiod_put(desc);
                return ERR_PTR(ret);
        }
  
        return desc;
  }
 -EXPORT_SYMBOL(gpiod_get_from_of_node);
 +EXPORT_SYMBOL_GPL(gpiod_get_index);
  
  /**
   * fwnode_get_named_gpiod - obtain a GPIO from firmware node
@@@ -4643,7 -4432,7 +4644,7 @@@ int gpiod_hog(struct gpio_desc *desc, c
        struct gpio_chip *chip;
        struct gpio_desc *local_desc;
        int hwnum;
 -      int status;
 +      int ret;
  
        chip = gpiod_to_chip(desc);
        hwnum = gpio_chip_hwgpio(desc);
@@@ -4651,10 -4440,10 +4652,10 @@@
        local_desc = gpiochip_request_own_desc(chip, hwnum, name,
                                               lflags, dflags);
        if (IS_ERR(local_desc)) {
 -              status = PTR_ERR(local_desc);
 +              ret = PTR_ERR(local_desc);
                pr_err("requesting hog GPIO %s (chip %s, offset %d) failed, %d\n",
 -                     name, chip->label, hwnum, status);
 -              return status;
 +                     name, chip->label, hwnum, ret);
 +              return ret;
        }
  
        /* Mark GPIO as hogged so it can be identified and removed later */

diff --combined drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index ff84d1afd229d34f50be3564277222221342582a,09042fca62b8e71b92110c053191b39950e5a3c1..d8a804b9f9582985128dd36fc5454016ec89cda1
--- 1/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
--- 2/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@@ -21,6 -21,13 +21,13 @@@
  #include "../pinctrl-utils.h"
  #include "pinctrl-aspeed.h"
  
+ /* Wrap some of the common macros for clarity */
+ #define SIG_EXPR_DECL_SINGLE(sig, func, ...) \
+       SIG_EXPR_DECL(sig, func, func, __VA_ARGS__)
+ 
+ #define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG
+ #define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG
+ 
  /*
   * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
   * references registers by the device/offset mnemonic. The register macros
@@@ -63,9 -70,9 +70,9 @@@ SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SI
  SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
  
  #define D13 2
- SIG_EXPR_LIST_DECL_SINGLE(SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15));
- SIG_EXPR_LIST_DECL_SINGLE(TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2));
- MS_PIN_DECL(D13, GPIOA2, SPI1CS1, TIMER3);
+ SIG_EXPR_LIST_DECL_SINGLE(D13, SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15));
+ SIG_EXPR_LIST_DECL_SINGLE(D13, TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2));
+ PIN_DECL_2(D13, GPIOA2, SPI1CS1, TIMER3);
  FUNC_GROUP_DECL(SPI1CS1, D13);
  FUNC_GROUP_DECL(TIMER3, D13);
  
@@@ -75,16 -82,16 +82,16 @@@ SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_
  #define I2C9_DESC     SIG_DESC_SET(SCU90, 22)
  
  #define C14 4
- SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC, COND1);
- SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1);
- MS_PIN_DECL(C14, GPIOA4, SCL9, TIMER5);
+ SIG_EXPR_LIST_DECL_SINGLE(C14, SCL9, I2C9, I2C9_DESC, COND1);
+ SIG_EXPR_LIST_DECL_SINGLE(C14, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1);
+ PIN_DECL_2(C14, GPIOA4, SCL9, TIMER5);
  
  FUNC_GROUP_DECL(TIMER5, C14);
  
  #define A13 5
- SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC, COND1);
- SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1);
- MS_PIN_DECL(A13, GPIOA5, SDA9, TIMER6);
+ SIG_EXPR_LIST_DECL_SINGLE(A13, SDA9, I2C9, I2C9_DESC, COND1);
+ SIG_EXPR_LIST_DECL_SINGLE(A13, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1);
+ PIN_DECL_2(A13, GPIOA5, SDA9, TIMER6);
  
  FUNC_GROUP_DECL(TIMER6, A13);
  
@@@ -93,16 -100,16 +100,16 @@@ FUNC_GROUP_DECL(I2C9, C14, A13)
  #define MDIO2_DESC    SIG_DESC_SET(SCU90, 2)
  
  #define C13 6
- SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC, COND1);
- SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1);
- MS_PIN_DECL(C13, GPIOA6, MDC2, TIMER7);
+ SIG_EXPR_LIST_DECL_SINGLE(C13, MDC2, MDIO2, MDIO2_DESC, COND1);
+ SIG_EXPR_LIST_DECL_SINGLE(C13, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1);
+ PIN_DECL_2(C13, GPIOA6, MDC2, TIMER7);
  
  FUNC_GROUP_DECL(TIMER7, C13);
  
  #define B13 7
- SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC, COND1);
- SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1);
- MS_PIN_DECL(B13, GPIOA7, MDIO2, TIMER8);
+ SIG_EXPR_LIST_DECL_SINGLE(B13, MDIO2, MDIO2, MDIO2_DESC, COND1);
+ SIG_EXPR_LIST_DECL_SINGLE(B13, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1);
+ PIN_DECL_2(B13, GPIOA7, MDIO2, TIMER8);
  
  FUNC_GROUP_DECL(TIMER8, B13);
  
@@@ -125,9 -132,9 +132,9 @@@ SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_
  
  #define H21 13
  #define H21_DESC      SIG_DESC_SET(SCU80, 13)
- SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H21_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H21_DESC);
- MS_PIN_DECL(H21, GPIOB5, LPCPD, LPCSMI);
+ SIG_EXPR_LIST_DECL_SINGLE(H21, LPCPD, LPCPD, H21_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(H21, LPCSMI, LPCSMI, H21_DESC);
+ PIN_DECL_2(H21, GPIOB5, LPCPD, LPCSMI);
  FUNC_GROUP_DECL(LPCPD, H21);
  FUNC_GROUP_DECL(LPCSMI, H21);
  
@@@ -141,53 -148,53 +148,53 @@@ GPIO_PIN_DECL(H20, GPIOB7)
  
  #define C12 16
  #define I2C10_DESC    SIG_DESC_SET(SCU90, 23)
- SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC);
- MS_PIN_DECL(C12, GPIOC0, SD1CLK, SCL10);
+ SIG_EXPR_LIST_DECL_SINGLE(C12, SD1CLK, SD1, SD1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(C12, SCL10, I2C10, I2C10_DESC);
+ PIN_DECL_2(C12, GPIOC0, SD1CLK, SCL10);
  
  #define A12 17
- SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC);
- MS_PIN_DECL(A12, GPIOC1, SD1CMD, SDA10);
+ SIG_EXPR_LIST_DECL_SINGLE(A12, SD1CMD, SD1, SD1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(A12, SDA10, I2C10, I2C10_DESC);
+ PIN_DECL_2(A12, GPIOC1, SD1CMD, SDA10);
  
  FUNC_GROUP_DECL(I2C10, C12, A12);
  
  #define B12 18
  #define I2C11_DESC    SIG_DESC_SET(SCU90, 24)
- SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC);
- MS_PIN_DECL(B12, GPIOC2, SD1DAT0, SCL11);
+ SIG_EXPR_LIST_DECL_SINGLE(B12, SD1DAT0, SD1, SD1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(B12, SCL11, I2C11, I2C11_DESC);
+ PIN_DECL_2(B12, GPIOC2, SD1DAT0, SCL11);
  
  #define D9  19
- SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC);
- MS_PIN_DECL(D9, GPIOC3, SD1DAT1, SDA11);
+ SIG_EXPR_LIST_DECL_SINGLE(D9, SD1DAT1, SD1, SD1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(D9, SDA11, I2C11, I2C11_DESC);
+ PIN_DECL_2(D9, GPIOC3, SD1DAT1, SDA11);
  
  FUNC_GROUP_DECL(I2C11, B12, D9);
  
  #define D10 20
  #define I2C12_DESC    SIG_DESC_SET(SCU90, 25)
- SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC);
- MS_PIN_DECL(D10, GPIOC4, SD1DAT2, SCL12);
+ SIG_EXPR_LIST_DECL_SINGLE(D10, SD1DAT2, SD1, SD1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(D10, SCL12, I2C12, I2C12_DESC);
+ PIN_DECL_2(D10, GPIOC4, SD1DAT2, SCL12);
  
  #define E12 21
- SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC);
- MS_PIN_DECL(E12, GPIOC5, SD1DAT3, SDA12);
+ SIG_EXPR_LIST_DECL_SINGLE(E12, SD1DAT3, SD1, SD1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(E12, SDA12, I2C12, I2C12_DESC);
+ PIN_DECL_2(E12, GPIOC5, SD1DAT3, SDA12);
  
  FUNC_GROUP_DECL(I2C12, D10, E12);
  
  #define C11 22
  #define I2C13_DESC    SIG_DESC_SET(SCU90, 26)
- SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC);
- MS_PIN_DECL(C11, GPIOC6, SD1CD, SCL13);
+ SIG_EXPR_LIST_DECL_SINGLE(C11, SD1CD, SD1, SD1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(C11, SCL13, I2C13, I2C13_DESC);
+ PIN_DECL_2(C11, GPIOC6, SD1CD, SCL13);
  
  #define B11 23
- SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC);
- MS_PIN_DECL(B11, GPIOC7, SD1WP, SDA13);
+ SIG_EXPR_LIST_DECL_SINGLE(B11, SD1WP, SD1, SD1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(B11, SDA13, I2C13, I2C13_DESC);
+ PIN_DECL_2(B11, GPIOC7, SD1WP, SDA13);
  
  FUNC_GROUP_DECL(I2C13, C11, B11);
  FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11);
@@@ -197,72 -204,72 +204,72 @@@
  #define GPID_DESC       SIG_DESC_SET(HW_STRAP1, 21)
  
  #define F19 24
- SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC);
- SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC);
- SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID);
- MS_PIN_DECL(F19, GPIOD0, SD2CLK, GPID0IN);
+ SIG_EXPR_LIST_DECL_SINGLE(F19, SD2CLK, SD2, SD2_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(F19, GPID0IN, GPID0, GPID);
+ PIN_DECL_2(F19, GPIOD0, SD2CLK, GPID0IN);
  
  #define E21 25
- SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC);
- SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC);
- SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID);
- MS_PIN_DECL(E21, GPIOD1, SD2CMD, GPID0OUT);
+ SIG_EXPR_LIST_DECL_SINGLE(E21, SD2CMD, SD2, SD2_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(E21, GPID0OUT, GPID0, GPID);
+ PIN_DECL_2(E21, GPIOD1, SD2CMD, GPID0OUT);
  
  FUNC_GROUP_DECL(GPID0, F19, E21);
  
  #define GPID2_DESC      SIG_DESC_SET(SCU8C, 9)
  
  #define F20 26
- SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC);
- SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC);
- SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID);
- MS_PIN_DECL(F20, GPIOD2, SD2DAT0, GPID2IN);
+ SIG_EXPR_LIST_DECL_SINGLE(F20, SD2DAT0, SD2, SD2_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(F20, GPID2IN, GPID2, GPID);
+ PIN_DECL_2(F20, GPIOD2, SD2DAT0, GPID2IN);
  
  #define D20 27
- SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC);
- SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC);
- SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID);
- MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT);
+ SIG_EXPR_LIST_DECL_SINGLE(D20, SD2DAT1, SD2, SD2_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(D20, GPID2OUT, GPID2, GPID);
+ PIN_DECL_2(D20, GPIOD3, SD2DAT1, GPID2OUT);
  
  FUNC_GROUP_DECL(GPID2, F20, D20);
  
  #define GPID4_DESC      SIG_DESC_SET(SCU8C, 10)
  
  #define D21 28
- SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC);
- SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC);
- SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID);
- MS_PIN_DECL(D21, GPIOD4, SD2DAT2, GPID4IN);
+ SIG_EXPR_LIST_DECL_SINGLE(D21, SD2DAT2, SD2, SD2_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(D21, GPID4IN, GPID4, GPID);
+ PIN_DECL_2(D21, GPIOD4, SD2DAT2, GPID4IN);
  
  #define E20 29
- SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC);
- SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC);
- SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID);
- MS_PIN_DECL(E20, GPIOD5, SD2DAT3, GPID4OUT);
+ SIG_EXPR_LIST_DECL_SINGLE(E20, SD2DAT3, SD2, SD2_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(E20, GPID4OUT, GPID4, GPID);
+ PIN_DECL_2(E20, GPIOD5, SD2DAT3, GPID4OUT);
  
  FUNC_GROUP_DECL(GPID4, D21, E20);
  
  #define GPID6_DESC      SIG_DESC_SET(SCU8C, 11)
  
  #define G18 30
- SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC);
- SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC);
- SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID);
- MS_PIN_DECL(G18, GPIOD6, SD2CD, GPID6IN);
+ SIG_EXPR_LIST_DECL_SINGLE(G18, SD2CD, SD2, SD2_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(G18, GPID6IN, GPID6, GPID);
+ PIN_DECL_2(G18, GPIOD6, SD2CD, GPID6IN);
  
  #define C21 31
- SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC);
- SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC);
- SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID);
- MS_PIN_DECL(C21, GPIOD7, SD2WP, GPID6OUT);
+ SIG_EXPR_LIST_DECL_SINGLE(C21, SD2WP, SD2, SD2_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC);
+ SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(C21, GPID6OUT, GPID6, GPID);
+ PIN_DECL_2(C21, GPIOD7, SD2WP, GPID6OUT);
  
  FUNC_GROUP_DECL(GPID6, G18, C21);
  FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21);
@@@ -271,19 -278,19 +278,19 @@@
  #define GPIE0_DESC    SIG_DESC_SET(SCU8C, 12)
  
  #define B20 32
- SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
- SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC);
- SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE);
- MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN);
+ SIG_EXPR_LIST_DECL_SINGLE(B20, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
+ SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC);
+ SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(B20, GPIE0IN, GPIE0, GPIE);
+ PIN_DECL_2(B20, GPIOE0, NCTS3, GPIE0IN);
  FUNC_GROUP_DECL(NCTS3, B20);
  
  #define C20 33
- SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
- SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC);
- SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE);
- MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
+ SIG_EXPR_LIST_DECL_SINGLE(C20, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
+ SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC);
+ SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(C20, GPIE0OUT, GPIE0, GPIE);
+ PIN_DECL_2(C20, GPIOE1, NDCD3, GPIE0OUT);
  FUNC_GROUP_DECL(NDCD3, C20);
  
  FUNC_GROUP_DECL(GPIE0, B20, C20);
@@@ -291,20 -298,20 +298,20 @@@
  #define GPIE2_DESC    SIG_DESC_SET(SCU8C, 13)
  
  #define F18 34
- SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
- SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC);
- SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE);
- MS_PIN_DECL(F18, GPIOE2, NDSR3, GPIE2IN);
+ SIG_EXPR_LIST_DECL_SINGLE(F18, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
+ SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC);
+ SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(F18, GPIE2IN, GPIE2, GPIE);
+ PIN_DECL_2(F18, GPIOE2, NDSR3, GPIE2IN);
  FUNC_GROUP_DECL(NDSR3, F18);
  
  
  #define F17 35
- SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
- SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC);
- SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE);
- MS_PIN_DECL(F17, GPIOE3, NRI3, GPIE2OUT);
+ SIG_EXPR_LIST_DECL_SINGLE(F17, NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
+ SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC);
+ SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(F17, GPIE2OUT, GPIE2, GPIE);
+ PIN_DECL_2(F17, GPIOE3, NRI3, GPIE2OUT);
  FUNC_GROUP_DECL(NRI3, F17);
  
  FUNC_GROUP_DECL(GPIE2, F18, F17);
@@@ -312,19 -319,19 +319,19 @@@
  #define GPIE4_DESC    SIG_DESC_SET(SCU8C, 14)
  
  #define E18 36
- SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
- SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC);
- SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE);
- MS_PIN_DECL(E18, GPIOE4, NDTR3, GPIE4IN);
+ SIG_EXPR_LIST_DECL_SINGLE(E18, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
+ SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC);
+ SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(E18, GPIE4IN, GPIE4, GPIE);
+ PIN_DECL_2(E18, GPIOE4, NDTR3, GPIE4IN);
  FUNC_GROUP_DECL(NDTR3, E18);
  
  #define D19 37
- SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
- SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC);
- SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE);
- MS_PIN_DECL(D19, GPIOE5, NRTS3, GPIE4OUT);
+ SIG_EXPR_LIST_DECL_SINGLE(D19, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
+ SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC);
+ SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(D19, GPIE4OUT, GPIE4, GPIE);
+ PIN_DECL_2(D19, GPIOE5, NRTS3, GPIE4OUT);
  FUNC_GROUP_DECL(NRTS3, D19);
  
  FUNC_GROUP_DECL(GPIE4, E18, D19);
@@@ -332,19 -339,19 +339,19 @@@
  #define GPIE6_DESC    SIG_DESC_SET(SCU8C, 15)
  
  #define A20 38
- SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
- SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC);
- SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE);
- MS_PIN_DECL(A20, GPIOE6, TXD3, GPIE6IN);
+ SIG_EXPR_LIST_DECL_SINGLE(A20, TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
+ SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC);
+ SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(A20, GPIE6IN, GPIE6, GPIE);
+ PIN_DECL_2(A20, GPIOE6, TXD3, GPIE6IN);
  FUNC_GROUP_DECL(TXD3, A20);
  
  #define B19 39
- SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
- SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC);
- SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC);
- SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE);
- MS_PIN_DECL(B19, GPIOE7, RXD3, GPIE6OUT);
+ SIG_EXPR_LIST_DECL_SINGLE(B19, RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
+ SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC);
+ SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(B19, GPIE6OUT, GPIE6, GPIE);
+ PIN_DECL_2(B19, GPIOE7, RXD3, GPIE6OUT);
  FUNC_GROUP_DECL(RXD3, B19);
  
  FUNC_GROUP_DECL(GPIE6, A20, B19);
@@@ -353,112 -360,112 +360,112 @@@
  #define LPCPLUS_DESC  SIG_DESC_SET(SCU90, 30)
  
  #define J19 40
- SIG_EXPR_DECL(LHAD0, LPCHC, LPCHC_DESC);
- SIG_EXPR_DECL(LHAD0, LPCPLUS, LPCPLUS_DESC);
- SIG_EXPR_LIST_DECL_DUAL(LHAD0, LPCHC, LPCPLUS);
- SIG_EXPR_LIST_DECL_SINGLE(NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24));
- MS_PIN_DECL(J19, GPIOF0, LHAD0, NCTS4);
+ SIG_EXPR_DECL_SINGLE(LHAD0, LPCHC, LPCHC_DESC);
+ SIG_EXPR_DECL_SINGLE(LHAD0, LPCPLUS, LPCPLUS_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(J19, LHAD0, LPCHC, LPCPLUS);
+ SIG_EXPR_LIST_DECL_SINGLE(J19, NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24));
+ PIN_DECL_2(J19, GPIOF0, LHAD0, NCTS4);
  FUNC_GROUP_DECL(NCTS4, J19);
  
  #define J18 41
- SIG_EXPR_DECL(LHAD1, LPCHC, LPCHC_DESC);
- SIG_EXPR_DECL(LHAD1, LPCPLUS, LPCPLUS_DESC);
- SIG_EXPR_LIST_DECL_DUAL(LHAD1, LPCHC, LPCPLUS);
- SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
- MS_PIN_DECL(J18, GPIOF1, LHAD1, NDCD4);
+ SIG_EXPR_DECL_SINGLE(LHAD1, LPCHC, LPCHC_DESC);
+ SIG_EXPR_DECL_SINGLE(LHAD1, LPCPLUS, LPCPLUS_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(J18, LHAD1, LPCHC, LPCPLUS);
+ SIG_EXPR_LIST_DECL_SINGLE(J18, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
+ PIN_DECL_2(J18, GPIOF1, LHAD1, NDCD4);
  FUNC_GROUP_DECL(NDCD4, J18);
  
  #define B22 42
- SIG_EXPR_DECL(LHAD2, LPCHC, LPCHC_DESC);
- SIG_EXPR_DECL(LHAD2, LPCPLUS, LPCPLUS_DESC);
- SIG_EXPR_LIST_DECL_DUAL(LHAD2, LPCHC, LPCPLUS);
- SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
- MS_PIN_DECL(B22, GPIOF2, LHAD2, NDSR4);
+ SIG_EXPR_DECL_SINGLE(LHAD2, LPCHC, LPCHC_DESC);
+ SIG_EXPR_DECL_SINGLE(LHAD2, LPCPLUS, LPCPLUS_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(B22, LHAD2, LPCHC, LPCPLUS);
+ SIG_EXPR_LIST_DECL_SINGLE(B22, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
+ PIN_DECL_2(B22, GPIOF2, LHAD2, NDSR4);
  FUNC_GROUP_DECL(NDSR4, B22);
  
  #define B21 43
- SIG_EXPR_DECL(LHAD3, LPCHC, LPCHC_DESC);
- SIG_EXPR_DECL(LHAD3, LPCPLUS, LPCPLUS_DESC);
- SIG_EXPR_LIST_DECL_DUAL(LHAD3, LPCHC, LPCPLUS);
- SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
- MS_PIN_DECL(B21, GPIOF3, LHAD3, NRI4);
+ SIG_EXPR_DECL_SINGLE(LHAD3, LPCHC, LPCHC_DESC);
+ SIG_EXPR_DECL_SINGLE(LHAD3, LPCPLUS, LPCPLUS_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(B21, LHAD3, LPCHC, LPCPLUS);
+ SIG_EXPR_LIST_DECL_SINGLE(B21, NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
+ PIN_DECL_2(B21, GPIOF3, LHAD3, NRI4);
  FUNC_GROUP_DECL(NRI4, B21);
  
  #define A21 44
- SIG_EXPR_DECL(LHCLK, LPCHC, LPCHC_DESC);
- SIG_EXPR_DECL(LHCLK, LPCPLUS, LPCPLUS_DESC);
- SIG_EXPR_LIST_DECL_DUAL(LHCLK, LPCHC, LPCPLUS);
- SIG_EXPR_LIST_DECL_SINGLE(NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28));
- MS_PIN_DECL(A21, GPIOF4, LHCLK, NDTR4);
+ SIG_EXPR_DECL_SINGLE(LHCLK, LPCHC, LPCHC_DESC);
+ SIG_EXPR_DECL_SINGLE(LHCLK, LPCPLUS, LPCPLUS_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(A21, LHCLK, LPCHC, LPCPLUS);
+ SIG_EXPR_LIST_DECL_SINGLE(A21, NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28));
+ PIN_DECL_2(A21, GPIOF4, LHCLK, NDTR4);
  FUNC_GROUP_DECL(NDTR4, A21);
  
  #define H19 45
- SIG_EXPR_DECL(LHFRAME, LPCHC, LPCHC_DESC);
- SIG_EXPR_DECL(LHFRAME, LPCPLUS, LPCPLUS_DESC);
- SIG_EXPR_LIST_DECL_DUAL(LHFRAME, LPCHC, LPCPLUS);
- SIG_EXPR_LIST_DECL_SINGLE(NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29));
- MS_PIN_DECL(H19, GPIOF5, LHFRAME, NRTS4);
+ SIG_EXPR_DECL_SINGLE(LHFRAME, LPCHC, LPCHC_DESC);
+ SIG_EXPR_DECL_SINGLE(LHFRAME, LPCPLUS, LPCPLUS_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(H19, LHFRAME, LPCHC, LPCPLUS);
+ SIG_EXPR_LIST_DECL_SINGLE(H19, NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29));
+ PIN_DECL_2(H19, GPIOF5, LHFRAME, NRTS4);
  FUNC_GROUP_DECL(NRTS4, H19);
  
  #define G17 46
- SIG_EXPR_LIST_DECL_SINGLE(LHSIRQ, LPCHC, LPCHC_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(TXD4, TXD4, SIG_DESC_SET(SCU80, 30));
- MS_PIN_DECL(G17, GPIOF6, LHSIRQ, TXD4);
+ SIG_EXPR_LIST_DECL_SINGLE(G17, LHSIRQ, LPCHC, LPCHC_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(G17, TXD4, TXD4, SIG_DESC_SET(SCU80, 30));
+ PIN_DECL_2(G17, GPIOF6, LHSIRQ, TXD4);
  FUNC_GROUP_DECL(TXD4, G17);
  
  #define H18 47
- SIG_EXPR_DECL(LHRST, LPCHC, LPCHC_DESC);
- SIG_EXPR_DECL(LHRST, LPCPLUS, LPCPLUS_DESC);
- SIG_EXPR_LIST_DECL_DUAL(LHRST, LPCHC, LPCPLUS);
- SIG_EXPR_LIST_DECL_SINGLE(RXD4, RXD4, SIG_DESC_SET(SCU80, 31));
- MS_PIN_DECL(H18, GPIOF7, LHRST, RXD4);
+ SIG_EXPR_DECL_SINGLE(LHRST, LPCHC, LPCHC_DESC);
+ SIG_EXPR_DECL_SINGLE(LHRST, LPCPLUS, LPCPLUS_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(H18, LHRST, LPCHC, LPCPLUS);
+ SIG_EXPR_LIST_DECL_SINGLE(H18, RXD4, RXD4, SIG_DESC_SET(SCU80, 31));
+ PIN_DECL_2(H18, GPIOF7, LHRST, RXD4);
  FUNC_GROUP_DECL(RXD4, H18);
  
  FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18);
  FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18);
  
  #define A19 48
- SIG_EXPR_LIST_DECL_SINGLE(SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0));
- SS_PIN_DECL(A19, GPIOG0, SGPS1CK);
+ SIG_EXPR_LIST_DECL_SINGLE(A19, SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0));
+ PIN_DECL_1(A19, GPIOG0, SGPS1CK);
  
  #define E19 49
- SIG_EXPR_LIST_DECL_SINGLE(SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1));
- SS_PIN_DECL(E19, GPIOG1, SGPS1LD);
+ SIG_EXPR_LIST_DECL_SINGLE(E19, SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1));
+ PIN_DECL_1(E19, GPIOG1, SGPS1LD);
  
  #define C19 50
- SIG_EXPR_LIST_DECL_SINGLE(SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2));
- SS_PIN_DECL(C19, GPIOG2, SGPS1I0);
+ SIG_EXPR_LIST_DECL_SINGLE(C19, SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2));
+ PIN_DECL_1(C19, GPIOG2, SGPS1I0);
  
  #define E16 51
- SIG_EXPR_LIST_DECL_SINGLE(SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3));
- SS_PIN_DECL(E16, GPIOG3, SGPS1I1);
+ SIG_EXPR_LIST_DECL_SINGLE(E16, SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3));
+ PIN_DECL_1(E16, GPIOG3, SGPS1I1);
  
  FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16);
  
  #define SGPS2_DESC    SIG_DESC_SET(SCU94, 12)
  
  #define E17 52
- SIG_EXPR_LIST_DECL_SINGLE(SGPS2CK, SGPS2, COND1, SGPS2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4));
- MS_PIN_DECL(E17, GPIOG4, SGPS2CK, SALT1);
+ SIG_EXPR_LIST_DECL_SINGLE(E17, SGPS2CK, SGPS2, COND1, SGPS2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(E17, SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4));
+ PIN_DECL_2(E17, GPIOG4, SGPS2CK, SALT1);
  FUNC_GROUP_DECL(SALT1, E17);
  
  #define D16 53
- SIG_EXPR_LIST_DECL_SINGLE(SGPS2LD, SGPS2, COND1, SGPS2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5));
- MS_PIN_DECL(D16, GPIOG5, SGPS2LD, SALT2);
+ SIG_EXPR_LIST_DECL_SINGLE(D16, SGPS2LD, SGPS2, COND1, SGPS2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(D16, SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5));
+ PIN_DECL_2(D16, GPIOG5, SGPS2LD, SALT2);
  FUNC_GROUP_DECL(SALT2, D16);
  
  #define D15 54
- SIG_EXPR_LIST_DECL_SINGLE(SGPS2I0, SGPS2, COND1, SGPS2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6));
- MS_PIN_DECL(D15, GPIOG6, SGPS2I0, SALT3);
+ SIG_EXPR_LIST_DECL_SINGLE(D15, SGPS2I0, SGPS2, COND1, SGPS2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(D15, SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6));
+ PIN_DECL_2(D15, GPIOG6, SGPS2I0, SALT3);
  FUNC_GROUP_DECL(SALT3, D15);
  
  #define E14 55
- SIG_EXPR_LIST_DECL_SINGLE(SGPS2I1, SGPS2, COND1, SGPS2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7));
- MS_PIN_DECL(E14, GPIOG7, SGPS2I1, SALT4);
+ SIG_EXPR_LIST_DECL_SINGLE(E14, SGPS2I1, SGPS2, COND1, SGPS2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(E14, SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7));
+ PIN_DECL_2(E14, GPIOG7, SGPS2I1, SALT4);
  FUNC_GROUP_DECL(SALT4, E14);
  
  FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14);
@@@ -466,42 -473,42 +473,42 @@@
  #define UART6_DESC    SIG_DESC_SET(SCU90, 7)
  
  #define A18 56
- SIG_EXPR_LIST_DECL_SINGLE(DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5));
- SIG_EXPR_LIST_DECL_SINGLE(NCTS6, UART6, COND1, UART6_DESC);
- MS_PIN_DECL(A18, GPIOH0, DASHA18, NCTS6);
+ SIG_EXPR_LIST_DECL_SINGLE(A18, DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5));
+ SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, UART6, COND1, UART6_DESC);
+ PIN_DECL_2(A18, GPIOH0, DASHA18, NCTS6);
  
  #define B18 57
- SIG_EXPR_LIST_DECL_SINGLE(DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5));
- SIG_EXPR_LIST_DECL_SINGLE(NDCD6, UART6, COND1, UART6_DESC);
- MS_PIN_DECL(B18, GPIOH1, DASHB18, NDCD6);
+ SIG_EXPR_LIST_DECL_SINGLE(B18, DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5));
+ SIG_EXPR_LIST_DECL_SINGLE(B18, NDCD6, UART6, COND1, UART6_DESC);
+ PIN_DECL_2(B18, GPIOH1, DASHB18, NDCD6);
  
  #define D17 58
- SIG_EXPR_LIST_DECL_SINGLE(DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6));
- SIG_EXPR_LIST_DECL_SINGLE(NDSR6, UART6, COND1, UART6_DESC);
- MS_PIN_DECL(D17, GPIOH2, DASHD17, NDSR6);
+ SIG_EXPR_LIST_DECL_SINGLE(D17, DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6));
+ SIG_EXPR_LIST_DECL_SINGLE(D17, NDSR6, UART6, COND1, UART6_DESC);
+ PIN_DECL_2(D17, GPIOH2, DASHD17, NDSR6);
  
  #define C17 59
- SIG_EXPR_LIST_DECL_SINGLE(DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6));
- SIG_EXPR_LIST_DECL_SINGLE(NRI6, UART6, COND1, UART6_DESC);
- MS_PIN_DECL(C17, GPIOH3, DASHC17, NRI6);
+ SIG_EXPR_LIST_DECL_SINGLE(C17, DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6));
+ SIG_EXPR_LIST_DECL_SINGLE(C17, NRI6, UART6, COND1, UART6_DESC);
+ PIN_DECL_2(C17, GPIOH3, DASHC17, NRI6);
  
  #define A17 60
- SIG_EXPR_LIST_DECL_SINGLE(DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7));
- SIG_EXPR_LIST_DECL_SINGLE(NDTR6, UART6, COND1, UART6_DESC);
- MS_PIN_DECL(A17, GPIOH4, DASHA17, NDTR6);
+ SIG_EXPR_LIST_DECL_SINGLE(A17, DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7));
+ SIG_EXPR_LIST_DECL_SINGLE(A17, NDTR6, UART6, COND1, UART6_DESC);
+ PIN_DECL_2(A17, GPIOH4, DASHA17, NDTR6);
  
  #define B17 61
- SIG_EXPR_LIST_DECL_SINGLE(DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7));
- SIG_EXPR_LIST_DECL_SINGLE(NRTS6, UART6, COND1, UART6_DESC);
- MS_PIN_DECL(B17, GPIOH5, DASHB17, NRTS6);
+ SIG_EXPR_LIST_DECL_SINGLE(B17, DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7));
+ SIG_EXPR_LIST_DECL_SINGLE(B17, NRTS6, UART6, COND1, UART6_DESC);
+ PIN_DECL_2(B17, GPIOH5, DASHB17, NRTS6);
  
  #define A16 62
- SIG_EXPR_LIST_DECL_SINGLE(TXD6, UART6, COND1, UART6_DESC);
- SS_PIN_DECL(A16, GPIOH6, TXD6);
+ SIG_EXPR_LIST_DECL_SINGLE(A16, TXD6, UART6, COND1, UART6_DESC);
+ PIN_DECL_1(A16, GPIOH6, TXD6);
  
  #define D18 63
- SIG_EXPR_LIST_DECL_SINGLE(RXD6, UART6, COND1, UART6_DESC);
- SS_PIN_DECL(D18, GPIOH7, RXD6);
+ SIG_EXPR_LIST_DECL_SINGLE(D18, RXD6, UART6, COND1, UART6_DESC);
+ PIN_DECL_1(D18, GPIOH7, RXD6);
  
  FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18);
  
@@@ -513,70 -520,78 +520,78 @@@
        { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
  
  #define C18 64
- SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
- SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
- SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU);
- SS_PIN_DECL(C18, GPIOI0, SYSCS);
+ SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
+ SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(C18, SYSCS, SPI1DEBUG, SPI1PASSTHRU);
+ PIN_DECL_1(C18, GPIOI0, SYSCS);
  
  #define E15 65
- SIG_EXPR_DECL(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
- SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
- SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU);
- SS_PIN_DECL(E15, GPIOI1, SYSCK);
+ SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
+ SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(E15, SYSCK, SPI1DEBUG, SPI1PASSTHRU);
+ PIN_DECL_1(E15, GPIOI1, SYSCK);
  
  #define B16 66
- SIG_EXPR_DECL(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
- SIG_EXPR_DECL(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
- SIG_EXPR_LIST_DECL_DUAL(SYSMOSI, SPI1DEBUG, SPI1PASSTHRU);
- SS_PIN_DECL(B16, GPIOI2, SYSMOSI);
+ SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
+ SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(B16, SYSMOSI, SPI1DEBUG, SPI1PASSTHRU);
+ PIN_DECL_1(B16, GPIOI2, SYSMOSI);
  
  #define C16 67
- SIG_EXPR_DECL(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
- SIG_EXPR_DECL(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
- SIG_EXPR_LIST_DECL_DUAL(SYSMISO, SPI1DEBUG, SPI1PASSTHRU);
- SS_PIN_DECL(C16, GPIOI3, SYSMISO);
+ SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
+ SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(C16, SYSMISO, SPI1DEBUG, SPI1PASSTHRU);
+ PIN_DECL_1(C16, GPIOI3, SYSMISO);
  
  #define VB_DESC       SIG_DESC_SET(HW_STRAP1, 5)
  
  #define B15 68
- SIG_EXPR_DECL(SPI1CS0, SPI1, COND1, SPI1_DESC);
- SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
- SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
- SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1),
+ SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, COND1, SPI1_DESC);
+ SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
+ SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
+ SIG_EXPR_LIST_DECL(SPI1CS0, SPI1,
+                           SIG_EXPR_PTR(SPI1CS0, SPI1),
                            SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
                            SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
- SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOSROM, COND1, VB_DESC);
- MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS);
+ SIG_EXPR_LIST_ALIAS(B15, SPI1CS0, SPI1);
+ SIG_EXPR_LIST_DECL_SINGLE(B15, VBCS, VGABIOSROM, COND1, VB_DESC);
+ PIN_DECL_2(B15, GPIOI4, SPI1CS0, VBCS);
  
  #define C15 69
- SIG_EXPR_DECL(SPI1CK, SPI1, COND1, SPI1_DESC);
- SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
- SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
- SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1),
+ SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, COND1, SPI1_DESC);
+ SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
+ SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
+ SIG_EXPR_LIST_DECL(SPI1CK, SPI1,
+                           SIG_EXPR_PTR(SPI1CK, SPI1),
                            SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
                            SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
- SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOSROM, COND1, VB_DESC);
- MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK);
+ SIG_EXPR_LIST_ALIAS(C15, SPI1CK, SPI1);
+ SIG_EXPR_LIST_DECL_SINGLE(C15, VBCK, VGABIOSROM, COND1, VB_DESC);
+ PIN_DECL_2(C15, GPIOI5, SPI1CK, VBCK);
  
  #define A14 70
- SIG_EXPR_DECL(SPI1MOSI, SPI1, COND1, SPI1_DESC);
- SIG_EXPR_DECL(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
- SIG_EXPR_DECL(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
- SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1),
+ SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1, COND1, SPI1_DESC);
+ SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
+ SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
+ SIG_EXPR_LIST_DECL(SPI1MOSI, SPI1,
+                           SIG_EXPR_PTR(SPI1MOSI, SPI1),
                            SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG),
                            SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU));
- SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOSROM, COND1, VB_DESC);
- MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI);
+ SIG_EXPR_LIST_ALIAS(A14, SPI1MOSI, SPI1);
+ SIG_EXPR_LIST_DECL_SINGLE(A14, VBMOSI, VGABIOSROM, COND1, VB_DESC);
+ PIN_DECL_2(A14, GPIOI6, SPI1MOSI, VBMOSI);
  
  #define A15 71
- SIG_EXPR_DECL(SPI1MISO, SPI1, COND1, SPI1_DESC);
- SIG_EXPR_DECL(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
- SIG_EXPR_DECL(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
- SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1),
+ SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1, COND1, SPI1_DESC);
+ SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
+ SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
+ SIG_EXPR_LIST_DECL(SPI1MISO, SPI1,
+                           SIG_EXPR_PTR(SPI1MISO, SPI1),
                            SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG),
                            SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU));
- SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOSROM, COND1, VB_DESC);
- MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO);
+ SIG_EXPR_LIST_ALIAS(A15, SPI1MISO, SPI1);
+ SIG_EXPR_LIST_DECL_SINGLE(A15, VBMISO, VGABIOSROM, COND1, VB_DESC);
+ PIN_DECL_2(A15, GPIOI7, SPI1MISO, VBMISO);
  
  FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
  FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
@@@ -584,92 -599,92 +599,92 @@@ FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15
  FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
  
  #define R2 72
- SIG_EXPR_LIST_DECL_SINGLE(SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8));
- SS_PIN_DECL(R2, GPIOJ0, SGPMCK);
+ SIG_EXPR_LIST_DECL_SINGLE(R2, SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8));
+ PIN_DECL_1(R2, GPIOJ0, SGPMCK);
  
  #define L2 73
- SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
- SS_PIN_DECL(L2, GPIOJ1, SGPMLD);
+ SIG_EXPR_LIST_DECL_SINGLE(L2, SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
+ PIN_DECL_1(L2, GPIOJ1, SGPMLD);
  
  #define N3 74
- SIG_EXPR_LIST_DECL_SINGLE(SGPMO, SGPM, SIG_DESC_SET(SCU84, 10));
- SS_PIN_DECL(N3, GPIOJ2, SGPMO);
+ SIG_EXPR_LIST_DECL_SINGLE(N3, SGPMO, SGPM, SIG_DESC_SET(SCU84, 10));
+ PIN_DECL_1(N3, GPIOJ2, SGPMO);
  
  #define N4 75
- SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
- SS_PIN_DECL(N4, GPIOJ3, SGPMI);
+ SIG_EXPR_LIST_DECL_SINGLE(N4, SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
+ PIN_DECL_1(N4, GPIOJ3, SGPMI);
  
  FUNC_GROUP_DECL(SGPM, R2, L2, N3, N4);
  
  #define N5 76
- SIG_EXPR_LIST_DECL_SINGLE(VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12));
- SIG_EXPR_LIST_DECL_SINGLE(DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8));
- MS_PIN_DECL(N5, GPIOJ4, VGAHS, DASHN5);
+ SIG_EXPR_LIST_DECL_SINGLE(N5, VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12));
+ SIG_EXPR_LIST_DECL_SINGLE(N5, DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8));
+ PIN_DECL_2(N5, GPIOJ4, VGAHS, DASHN5);
  FUNC_GROUP_DECL(VGAHS, N5);
  
  #define R4 77
- SIG_EXPR_LIST_DECL_SINGLE(VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13));
- SIG_EXPR_LIST_DECL_SINGLE(DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8));
- MS_PIN_DECL(R4, GPIOJ5, VGAVS, DASHR4);
+ SIG_EXPR_LIST_DECL_SINGLE(R4, VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13));
+ SIG_EXPR_LIST_DECL_SINGLE(R4, DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8));
+ PIN_DECL_2(R4, GPIOJ5, VGAVS, DASHR4);
  FUNC_GROUP_DECL(VGAVS, R4);
  
  #define R3 78
- SIG_EXPR_LIST_DECL_SINGLE(DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14));
- SIG_EXPR_LIST_DECL_SINGLE(DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9));
- MS_PIN_DECL(R3, GPIOJ6, DDCCLK, DASHR3);
+ SIG_EXPR_LIST_DECL_SINGLE(R3, DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14));
+ SIG_EXPR_LIST_DECL_SINGLE(R3, DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9));
+ PIN_DECL_2(R3, GPIOJ6, DDCCLK, DASHR3);
  FUNC_GROUP_DECL(DDCCLK, R3);
  
  #define T3 79
- SIG_EXPR_LIST_DECL_SINGLE(DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15));
- SIG_EXPR_LIST_DECL_SINGLE(DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9));
- MS_PIN_DECL(T3, GPIOJ7, DDCDAT, DASHT3);
+ SIG_EXPR_LIST_DECL_SINGLE(T3, DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15));
+ SIG_EXPR_LIST_DECL_SINGLE(T3, DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9));
+ PIN_DECL_2(T3, GPIOJ7, DDCDAT, DASHT3);
  FUNC_GROUP_DECL(DDCDAT, T3);
  
  #define I2C5_DESC       SIG_DESC_SET(SCU90, 18)
  
  #define L3 80
- SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
- SS_PIN_DECL(L3, GPIOK0, SCL5);
+ SIG_EXPR_LIST_DECL_SINGLE(L3, SCL5, I2C5, I2C5_DESC);
+ PIN_DECL_1(L3, GPIOK0, SCL5);
  
  #define L4 81
- SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC);
- SS_PIN_DECL(L4, GPIOK1, SDA5);
+ SIG_EXPR_LIST_DECL_SINGLE(L4, SDA5, I2C5, I2C5_DESC);
+ PIN_DECL_1(L4, GPIOK1, SDA5);
  
  FUNC_GROUP_DECL(I2C5, L3, L4);
  
  #define I2C6_DESC       SIG_DESC_SET(SCU90, 19)
  
  #define L1 82
- SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC);
- SS_PIN_DECL(L1, GPIOK2, SCL6);
+ SIG_EXPR_LIST_DECL_SINGLE(L1, SCL6, I2C6, I2C6_DESC);
+ PIN_DECL_1(L1, GPIOK2, SCL6);
  
  #define N2 83
- SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC);
- SS_PIN_DECL(N2, GPIOK3, SDA6);
+ SIG_EXPR_LIST_DECL_SINGLE(N2, SDA6, I2C6, I2C6_DESC);
+ PIN_DECL_1(N2, GPIOK3, SDA6);
  
  FUNC_GROUP_DECL(I2C6, L1, N2);
  
  #define I2C7_DESC       SIG_DESC_SET(SCU90, 20)
  
  #define N1 84
- SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC);
- SS_PIN_DECL(N1, GPIOK4, SCL7);
+ SIG_EXPR_LIST_DECL_SINGLE(N1, SCL7, I2C7, I2C7_DESC);
+ PIN_DECL_1(N1, GPIOK4, SCL7);
  
  #define P1 85
- SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC);
- SS_PIN_DECL(P1, GPIOK5, SDA7);
+ SIG_EXPR_LIST_DECL_SINGLE(P1, SDA7, I2C7, I2C7_DESC);
+ PIN_DECL_1(P1, GPIOK5, SDA7);
  
  FUNC_GROUP_DECL(I2C7, N1, P1);
  
  #define I2C8_DESC       SIG_DESC_SET(SCU90, 21)
  
  #define P2 86
- SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC);
- SS_PIN_DECL(P2, GPIOK6, SCL8);
+ SIG_EXPR_LIST_DECL_SINGLE(P2, SCL8, I2C8, I2C8_DESC);
+ PIN_DECL_1(P2, GPIOK6, SCL8);
  
  #define R1 87
- SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC);
- SS_PIN_DECL(R1, GPIOK7, SDA8);
+ SIG_EXPR_LIST_DECL_SINGLE(R1, SDA8, I2C8, I2C8_DESC);
+ PIN_DECL_1(R1, GPIOK7, SDA8);
  
  FUNC_GROUP_DECL(I2C8, P2, R1);
  
@@@ -684,290 -699,290 +699,290 @@@ SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DE
  
  #define T1 89
  #define T1_DESC               SIG_DESC_SET(SCU84, 17)
- SIG_EXPR_LIST_DECL_SINGLE(VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2);
- SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T1_DESC, COND2);
- MS_PIN_DECL(T1, GPIOL1, VPIDE, NDCD1);
+ SIG_EXPR_LIST_DECL_SINGLE(T1, VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2);
+ SIG_EXPR_LIST_DECL_SINGLE(T1, NDCD1, NDCD1, T1_DESC, COND2);
+ PIN_DECL_2(T1, GPIOL1, VPIDE, NDCD1);
  FUNC_GROUP_DECL(NDCD1, T1);
  
  #define U1 90
  #define U1_DESC               SIG_DESC_SET(SCU84, 18)
- SIG_EXPR_LIST_DECL_SINGLE(DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U1_DESC);
- MS_PIN_DECL(U1, GPIOL2, DASHU1, NDSR1);
+ SIG_EXPR_LIST_DECL_SINGLE(U1, DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(U1, NDSR1, NDSR1, U1_DESC);
+ PIN_DECL_2(U1, GPIOL2, DASHU1, NDSR1);
  FUNC_GROUP_DECL(NDSR1, U1);
  
  #define U2 91
  #define U2_DESC               SIG_DESC_SET(SCU84, 19)
- SIG_EXPR_LIST_DECL_SINGLE(VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2);
- SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, U2_DESC, COND2);
- MS_PIN_DECL(U2, GPIOL3, VPIHS, NRI1);
+ SIG_EXPR_LIST_DECL_SINGLE(U2, VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2);
+ SIG_EXPR_LIST_DECL_SINGLE(U2, NRI1, NRI1, U2_DESC, COND2);
+ PIN_DECL_2(U2, GPIOL3, VPIHS, NRI1);
  FUNC_GROUP_DECL(NRI1, U2);
  
  #define P4 92
  #define P4_DESC               SIG_DESC_SET(SCU84, 20)
- SIG_EXPR_LIST_DECL_SINGLE(VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2);
- SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, P4_DESC, COND2);
- MS_PIN_DECL(P4, GPIOL4, VPIVS, NDTR1);
+ SIG_EXPR_LIST_DECL_SINGLE(P4, VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2);
+ SIG_EXPR_LIST_DECL_SINGLE(P4, NDTR1, NDTR1, P4_DESC, COND2);
+ PIN_DECL_2(P4, GPIOL4, VPIVS, NDTR1);
  FUNC_GROUP_DECL(NDTR1, P4);
  
  #define P3 93
  #define P3_DESC               SIG_DESC_SET(SCU84, 21)
- SIG_EXPR_LIST_DECL_SINGLE(VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2);
- SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, P3_DESC, COND2);
- MS_PIN_DECL(P3, GPIOL5, VPICLK, NRTS1);
+ SIG_EXPR_LIST_DECL_SINGLE(P3, VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2);
+ SIG_EXPR_LIST_DECL_SINGLE(P3, NRTS1, NRTS1, P3_DESC, COND2);
+ PIN_DECL_2(P3, GPIOL5, VPICLK, NRTS1);
  FUNC_GROUP_DECL(NRTS1, P3);
  
  #define V1 94
  #define V1_DESC               SIG_DESC_SET(SCU84, 22)
- SIG_EXPR_LIST_DECL_SINGLE(DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, V1_DESC, COND2);
- MS_PIN_DECL(V1, GPIOL6, DASHV1, TXD1);
+ SIG_EXPR_LIST_DECL_SINGLE(V1, DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(V1, TXD1, TXD1, V1_DESC, COND2);
+ PIN_DECL_2(V1, GPIOL6, DASHV1, TXD1);
  FUNC_GROUP_DECL(TXD1, V1);
  
  #define W1 95
  #define W1_DESC               SIG_DESC_SET(SCU84, 23)
- SIG_EXPR_LIST_DECL_SINGLE(DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, W1_DESC, COND2);
- MS_PIN_DECL(W1, GPIOL7, DASHW1, RXD1);
+ SIG_EXPR_LIST_DECL_SINGLE(W1, DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(W1, RXD1, RXD1, W1_DESC, COND2);
+ PIN_DECL_2(W1, GPIOL7, DASHW1, RXD1);
  FUNC_GROUP_DECL(RXD1, W1);
  
  #define Y1 96
  #define Y1_DESC               SIG_DESC_SET(SCU84, 24)
- SIG_EXPR_LIST_DECL_SINGLE(VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2);
- SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, Y1_DESC, COND2);
- MS_PIN_DECL(Y1, GPIOM0, VPIB2, NCTS2);
+ SIG_EXPR_LIST_DECL_SINGLE(Y1, VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2);
+ SIG_EXPR_LIST_DECL_SINGLE(Y1, NCTS2, NCTS2, Y1_DESC, COND2);
+ PIN_DECL_2(Y1, GPIOM0, VPIB2, NCTS2);
  FUNC_GROUP_DECL(NCTS2, Y1);
  
  #define AB2 97
  #define AB2_DESC      SIG_DESC_SET(SCU84, 25)
- SIG_EXPR_LIST_DECL_SINGLE(VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2);
- SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, AB2_DESC, COND2);
- MS_PIN_DECL(AB2, GPIOM1, VPIB3, NDCD2);
+ SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2);
+ SIG_EXPR_LIST_DECL_SINGLE(AB2, NDCD2, NDCD2, AB2_DESC, COND2);
+ PIN_DECL_2(AB2, GPIOM1, VPIB3, NDCD2);
  FUNC_GROUP_DECL(NDCD2, AB2);
  
  #define AA1 98
  #define AA1_DESC      SIG_DESC_SET(SCU84, 26)
- SIG_EXPR_LIST_DECL_SINGLE(VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2);
- SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, AA1_DESC, COND2);
- MS_PIN_DECL(AA1, GPIOM2, VPIB4, NDSR2);
+ SIG_EXPR_LIST_DECL_SINGLE(AA1, VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2);
+ SIG_EXPR_LIST_DECL_SINGLE(AA1, NDSR2, NDSR2, AA1_DESC, COND2);
+ PIN_DECL_2(AA1, GPIOM2, VPIB4, NDSR2);
  FUNC_GROUP_DECL(NDSR2, AA1);
  
  #define Y2 99
  #define Y2_DESC               SIG_DESC_SET(SCU84, 27)
- SIG_EXPR_LIST_DECL_SINGLE(VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2);
- SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, Y2_DESC, COND2);
- MS_PIN_DECL(Y2, GPIOM3, VPIB5, NRI2);
+ SIG_EXPR_LIST_DECL_SINGLE(Y2, VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2);
+ SIG_EXPR_LIST_DECL_SINGLE(Y2, NRI2, NRI2, Y2_DESC, COND2);
+ PIN_DECL_2(Y2, GPIOM3, VPIB5, NRI2);
  FUNC_GROUP_DECL(NRI2, Y2);
  
  #define AA2 100
  #define AA2_DESC      SIG_DESC_SET(SCU84, 28)
- SIG_EXPR_LIST_DECL_SINGLE(VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2);
- SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, AA2_DESC, COND2);
- MS_PIN_DECL(AA2, GPIOM4, VPIB6, NDTR2);
+ SIG_EXPR_LIST_DECL_SINGLE(AA2, VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2);
+ SIG_EXPR_LIST_DECL_SINGLE(AA2, NDTR2, NDTR2, AA2_DESC, COND2);
+ PIN_DECL_2(AA2, GPIOM4, VPIB6, NDTR2);
  FUNC_GROUP_DECL(NDTR2, AA2);
  
  #define P5 101
  #define P5_DESC       SIG_DESC_SET(SCU84, 29)
- SIG_EXPR_LIST_DECL_SINGLE(VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2);
- SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, P5_DESC, COND2);
- MS_PIN_DECL(P5, GPIOM5, VPIB7, NRTS2);
+ SIG_EXPR_LIST_DECL_SINGLE(P5, VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2);
+ SIG_EXPR_LIST_DECL_SINGLE(P5, NRTS2, NRTS2, P5_DESC, COND2);
+ PIN_DECL_2(P5, GPIOM5, VPIB7, NRTS2);
  FUNC_GROUP_DECL(NRTS2, P5);
  
  #define R5 102
  #define R5_DESC       SIG_DESC_SET(SCU84, 30)
- SIG_EXPR_LIST_DECL_SINGLE(VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2);
- SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, R5_DESC, COND2);
- MS_PIN_DECL(R5, GPIOM6, VPIB8, TXD2);
+ SIG_EXPR_LIST_DECL_SINGLE(R5, VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2);
+ SIG_EXPR_LIST_DECL_SINGLE(R5, TXD2, TXD2, R5_DESC, COND2);
+ PIN_DECL_2(R5, GPIOM6, VPIB8, TXD2);
  FUNC_GROUP_DECL(TXD2, R5);
  
  #define T5 103
  #define T5_DESC       SIG_DESC_SET(SCU84, 31)
- SIG_EXPR_LIST_DECL_SINGLE(VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2);
- SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, T5_DESC, COND2);
- MS_PIN_DECL(T5, GPIOM7, VPIB9, RXD2);
+ SIG_EXPR_LIST_DECL_SINGLE(T5, VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2);
+ SIG_EXPR_LIST_DECL_SINGLE(T5, RXD2, RXD2, T5_DESC, COND2);
+ PIN_DECL_2(T5, GPIOM7, VPIB9, RXD2);
  FUNC_GROUP_DECL(RXD2, T5);
  
  #define V2 104
  #define V2_DESC         SIG_DESC_SET(SCU88, 0)
- SIG_EXPR_LIST_DECL_SINGLE(DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, V2_DESC, COND2);
- MS_PIN_DECL(V2, GPION0, DASHN0, PWM0);
+ SIG_EXPR_LIST_DECL_SINGLE(V2, DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(V2, PWM0, PWM0, V2_DESC, COND2);
+ PIN_DECL_2(V2, GPION0, DASHN0, PWM0);
  FUNC_GROUP_DECL(PWM0, V2);
  
  #define W2 105
  #define W2_DESC         SIG_DESC_SET(SCU88, 1)
- SIG_EXPR_LIST_DECL_SINGLE(DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, W2_DESC, COND2);
- MS_PIN_DECL(W2, GPION1, DASHN1, PWM1);
+ SIG_EXPR_LIST_DECL_SINGLE(W2, DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(W2, PWM1, PWM1, W2_DESC, COND2);
+ PIN_DECL_2(W2, GPION1, DASHN1, PWM1);
  FUNC_GROUP_DECL(PWM1, W2);
  
  #define V3 106
  #define V3_DESC         SIG_DESC_SET(SCU88, 2)
- SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2);
- SIG_EXPR_DECL(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2);
- SIG_EXPR_LIST_DECL_DUAL(VPIG2, VPI24, VPIRSVD);
- SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, V3_DESC, COND2);
- MS_PIN_DECL(V3, GPION2, VPIG2, PWM2);
+ SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2);
+ SIG_EXPR_DECL_SINGLE(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2);
+ SIG_EXPR_LIST_DECL_DUAL(V3, VPIG2, VPI24, VPIRSVD);
+ SIG_EXPR_LIST_DECL_SINGLE(V3, PWM2, PWM2, V3_DESC, COND2);
+ PIN_DECL_2(V3, GPION2, VPIG2, PWM2);
  FUNC_GROUP_DECL(PWM2, V3);
  
  #define U3 107
  #define U3_DESC         SIG_DESC_SET(SCU88, 3)
- SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2);
- SIG_EXPR_DECL(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2);
- SIG_EXPR_LIST_DECL_DUAL(VPIG3, VPI24, VPIRSVD);
- SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, U3_DESC, COND2);
- MS_PIN_DECL(U3, GPION3, VPIG3, PWM3);
+ SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2);
+ SIG_EXPR_DECL_SINGLE(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2);
+ SIG_EXPR_LIST_DECL_DUAL(U3, VPIG3, VPI24, VPIRSVD);
+ SIG_EXPR_LIST_DECL_SINGLE(U3, PWM3, PWM3, U3_DESC, COND2);
+ PIN_DECL_2(U3, GPION3, VPIG3, PWM3);
  FUNC_GROUP_DECL(PWM3, U3);
  
  #define W3 108
  #define W3_DESC         SIG_DESC_SET(SCU88, 4)
- SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2);
- SIG_EXPR_DECL(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2);
- SIG_EXPR_LIST_DECL_DUAL(VPIG4, VPI24, VPIRSVD);
- SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W3_DESC, COND2);
- MS_PIN_DECL(W3, GPION4, VPIG4, PWM4);
+ SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2);
+ SIG_EXPR_DECL_SINGLE(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2);
+ SIG_EXPR_LIST_DECL_DUAL(W3, VPIG4, VPI24, VPIRSVD);
+ SIG_EXPR_LIST_DECL_SINGLE(W3, PWM4, PWM4, W3_DESC, COND2);
+ PIN_DECL_2(W3, GPION4, VPIG4, PWM4);
  FUNC_GROUP_DECL(PWM4, W3);
  
  #define AA3 109
  #define AA3_DESC        SIG_DESC_SET(SCU88, 5)
- SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2);
- SIG_EXPR_DECL(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2);
- SIG_EXPR_LIST_DECL_DUAL(VPIG5, VPI24, VPIRSVD);
- SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, AA3_DESC, COND2);
- MS_PIN_DECL(AA3, GPION5, VPIG5, PWM5);
+ SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2);
+ SIG_EXPR_DECL_SINGLE(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2);
+ SIG_EXPR_LIST_DECL_DUAL(AA3, VPIG5, VPI24, VPIRSVD);
+ SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM5, PWM5, AA3_DESC, COND2);
+ PIN_DECL_2(AA3, GPION5, VPIG5, PWM5);
  FUNC_GROUP_DECL(PWM5, AA3);
  
  #define Y3 110
  #define Y3_DESC         SIG_DESC_SET(SCU88, 6)
- SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI24, VPI24_DESC, Y3_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, Y3_DESC, COND2);
- MS_PIN_DECL(Y3, GPION6, VPIG6, PWM6);
+ SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG6, VPI24, VPI24_DESC, Y3_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM6, PWM6, Y3_DESC, COND2);
+ PIN_DECL_2(Y3, GPION6, VPIG6, PWM6);
  FUNC_GROUP_DECL(PWM6, Y3);
  
  #define T4 111
  #define T4_DESC         SIG_DESC_SET(SCU88, 7)
- SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI24, VPI24_DESC, T4_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2);
- MS_PIN_DECL(T4, GPION7, VPIG7, PWM7);
+ SIG_EXPR_LIST_DECL_SINGLE(T4, VPIG7, VPI24, VPI24_DESC, T4_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(T4, PWM7, PWM7, T4_DESC, COND2);
+ PIN_DECL_2(T4, GPION7, VPIG7, PWM7);
  FUNC_GROUP_DECL(PWM7, T4);
  
  #define U5 112
- SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8),
+ SIG_EXPR_LIST_DECL_SINGLE(U5, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8),
                          COND2);
- SS_PIN_DECL(U5, GPIOO0, VPIG8);
+ PIN_DECL_1(U5, GPIOO0, VPIG8);
  
  #define U4 113
- SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9),
+ SIG_EXPR_LIST_DECL_SINGLE(U4, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9),
                          COND2);
- SS_PIN_DECL(U4, GPIOO1, VPIG9);
+ PIN_DECL_1(U4, GPIOO1, VPIG9);
  
  #define V5 114
- SIG_EXPR_LIST_DECL_SINGLE(DASHV5, DASHV5, VPI_24_RSVD_DESC,
+ SIG_EXPR_LIST_DECL_SINGLE(V5, DASHV5, DASHV5, VPI_24_RSVD_DESC,
                          SIG_DESC_SET(SCU88, 10));
- SS_PIN_DECL(V5, GPIOO2, DASHV5);
+ PIN_DECL_1(V5, GPIOO2, DASHV5);
  
  #define AB4 115
- SIG_EXPR_LIST_DECL_SINGLE(DASHAB4, DASHAB4, VPI_24_RSVD_DESC,
+ SIG_EXPR_LIST_DECL_SINGLE(AB4, DASHAB4, DASHAB4, VPI_24_RSVD_DESC,
                          SIG_DESC_SET(SCU88, 11));
- SS_PIN_DECL(AB4, GPIOO3, DASHAB4);
+ PIN_DECL_1(AB4, GPIOO3, DASHAB4);
  
  #define AB3 116
- SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12),
-                         COND2);
- SS_PIN_DECL(AB3, GPIOO4, VPIR2);
+ SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR2, VPI24, VPI24_DESC,
+                         SIG_DESC_SET(SCU88, 12), COND2);
+ PIN_DECL_1(AB3, GPIOO4, VPIR2);
  
  #define Y4 117
- SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13),
-                         COND2);
- SS_PIN_DECL(Y4, GPIOO5, VPIR3);
+ SIG_EXPR_LIST_DECL_SINGLE(Y4, VPIR3, VPI24, VPI24_DESC,
+                         SIG_DESC_SET(SCU88, 13), COND2);
+ PIN_DECL_1(Y4, GPIOO5, VPIR3);
  
  #define AA4 118
- SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14),
-                         COND2);
- SS_PIN_DECL(AA4, GPIOO6, VPIR4);
+ SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR4, VPI24, VPI24_DESC,
+                         SIG_DESC_SET(SCU88, 14), COND2);
+ PIN_DECL_1(AA4, GPIOO6, VPIR4);
  
  #define W4 119
- SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15),
-                         COND2);
- SS_PIN_DECL(W4, GPIOO7, VPIR5);
+ SIG_EXPR_LIST_DECL_SINGLE(W4, VPIR5, VPI24, VPI24_DESC,
+                         SIG_DESC_SET(SCU88, 15), COND2);
+ PIN_DECL_1(W4, GPIOO7, VPIR5);
  
  #define V4 120
- SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16),
-                         COND2);
- SS_PIN_DECL(V4, GPIOP0, VPIR6);
+ SIG_EXPR_LIST_DECL_SINGLE(V4, VPIR6, VPI24, VPI24_DESC,
+                         SIG_DESC_SET(SCU88, 16), COND2);
+ PIN_DECL_1(V4, GPIOP0, VPIR6);
  
  #define W5 121
- SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17),
-                         COND2);
- SS_PIN_DECL(W5, GPIOP1, VPIR7);
+ SIG_EXPR_LIST_DECL_SINGLE(W5, VPIR7, VPI24, VPI24_DESC,
+                         SIG_DESC_SET(SCU88, 17), COND2);
+ PIN_DECL_1(W5, GPIOP1, VPIR7);
  
  #define AA5 122
- SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18),
-                         COND2);
- SS_PIN_DECL(AA5, GPIOP2, VPIR8);
+ SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR8, VPI24, VPI24_DESC,
+                         SIG_DESC_SET(SCU88, 18), COND2);
+ PIN_DECL_1(AA5, GPIOP2, VPIR8);
  
  #define AB5 123
- SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19),
-                         COND2);
- SS_PIN_DECL(AB5, GPIOP3, VPIR9);
+ SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR9, VPI24, VPI24_DESC,
+                         SIG_DESC_SET(SCU88, 19), COND2);
+ PIN_DECL_1(AB5, GPIOP3, VPIR9);
  
  FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3,
                U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5,
                AB5);
  
  #define Y6 124
- SIG_EXPR_LIST_DECL_SINGLE(DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28),
+ SIG_EXPR_LIST_DECL_SINGLE(Y6, DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28),
                          SIG_DESC_SET(SCU88, 20));
- SS_PIN_DECL(Y6, GPIOP4, DASHY6);
+ PIN_DECL_1(Y6, GPIOP4, DASHY6);
  
  #define Y5 125
- SIG_EXPR_LIST_DECL_SINGLE(DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28),
+ SIG_EXPR_LIST_DECL_SINGLE(Y5, DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28),
                          SIG_DESC_SET(SCU88, 21));
- SS_PIN_DECL(Y5, GPIOP5, DASHY5);
+ PIN_DECL_1(Y5, GPIOP5, DASHY5);
  
  #define W6 126
- SIG_EXPR_LIST_DECL_SINGLE(DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28),
+ SIG_EXPR_LIST_DECL_SINGLE(W6, DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28),
                          SIG_DESC_SET(SCU88, 22));
- SS_PIN_DECL(W6, GPIOP6, DASHW6);
+ PIN_DECL_1(W6, GPIOP6, DASHW6);
  
  #define V6 127
- SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28),
+ SIG_EXPR_LIST_DECL_SINGLE(V6, DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28),
                          SIG_DESC_SET(SCU88, 23));
- SS_PIN_DECL(V6, GPIOP7, DASHV6);
+ PIN_DECL_1(V6, GPIOP7, DASHV6);
  
  #define I2C3_DESC     SIG_DESC_SET(SCU90, 16)
  
  #define A11 128
- SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC);
- SS_PIN_DECL(A11, GPIOQ0, SCL3);
+ SIG_EXPR_LIST_DECL_SINGLE(A11, SCL3, I2C3, I2C3_DESC);
+ PIN_DECL_1(A11, GPIOQ0, SCL3);
  
  #define A10 129
- SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC);
- SS_PIN_DECL(A10, GPIOQ1, SDA3);
+ SIG_EXPR_LIST_DECL_SINGLE(A10, SDA3, I2C3, I2C3_DESC);
+ PIN_DECL_1(A10, GPIOQ1, SDA3);
  
  FUNC_GROUP_DECL(I2C3, A11, A10);
  
  #define I2C4_DESC     SIG_DESC_SET(SCU90, 17)
  
  #define A9 130
- SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC);
- SS_PIN_DECL(A9, GPIOQ2, SCL4);
+ SIG_EXPR_LIST_DECL_SINGLE(A9, SCL4, I2C4, I2C4_DESC);
+ PIN_DECL_1(A9, GPIOQ2, SCL4);
  
  #define B9 131
- SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC);
- SS_PIN_DECL(B9, GPIOQ3, SDA4);
+ SIG_EXPR_LIST_DECL_SINGLE(B9, SDA4, I2C4, I2C4_DESC);
+ PIN_DECL_1(B9, GPIOQ3, SDA4);
  
  FUNC_GROUP_DECL(I2C4, A9, B9);
  
  #define I2C14_DESC    SIG_DESC_SET(SCU90, 27)
  
  #define N21 132
- SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC);
- SS_PIN_DECL(N21, GPIOQ4, SCL14);
+ SIG_EXPR_LIST_DECL_SINGLE(N21, SCL14, I2C14, I2C14_DESC);
+ PIN_DECL_1(N21, GPIOQ4, SCL14);
  
  #define N22 133
- SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC);
- SS_PIN_DECL(N22, GPIOQ5, SDA14);
+ SIG_EXPR_LIST_DECL_SINGLE(N22, SDA14, I2C14, I2C14_DESC);
+ PIN_DECL_1(N22, GPIOQ5, SDA14);
  
  FUNC_GROUP_DECL(I2C14, N21, N22);
  
@@@ -996,12 -1011,12 +1011,12 @@@ SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SI
  SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2);
  
  #define D8 142
- SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
- SS_PIN_DECL(D8, GPIOR6, MDC1);
+ SIG_EXPR_LIST_DECL_SINGLE(D8, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
+ PIN_DECL_1(D8, GPIOR6, MDC1);
  
  #define E10 143
- SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
- SS_PIN_DECL(E10, GPIOR7, MDIO1);
+ SIG_EXPR_LIST_DECL_SINGLE(E10, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
+ PIN_DECL_1(E10, GPIOR7, MDIO1);
  
  FUNC_GROUP_DECL(MDIO1, D8, E10);
  
@@@ -1014,83 -1029,107 +1029,107 @@@
  
  #define V20 144
  #define V20_DESC      SIG_DESC_SET(SCU8C, 0)
- SIG_EXPR_DECL(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO),
-               SIG_EXPR_PTR(VPOB2, VPOOFF1), SIG_EXPR_PTR(VPOB2, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(SPI2CS1, SPI2CS1, V20_DESC);
- MS_PIN_DECL(V20, GPIOS0, VPOB2, SPI2CS1);
+ SIG_EXPR_DECL_SINGLE(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOB2, VPO,
+               SIG_EXPR_PTR(VPOB2, VPO),
+               SIG_EXPR_PTR(VPOB2, VPOOFF1),
+               SIG_EXPR_PTR(VPOB2, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(V20, VPOB2, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(V20, SPI2CS1, SPI2CS1, V20_DESC);
+ PIN_DECL_2(V20, GPIOS0, VPOB2, SPI2CS1);
  FUNC_GROUP_DECL(SPI2CS1, V20);
  
  #define U19 145
  #define U19_DESC      SIG_DESC_SET(SCU8C, 1)
- SIG_EXPR_DECL(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO),
-               SIG_EXPR_PTR(VPOB3, VPOOFF1), SIG_EXPR_PTR(VPOB3, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(BMCINT, BMCINT, U19_DESC);
- MS_PIN_DECL(U19, GPIOS1, VPOB3, BMCINT);
+ SIG_EXPR_DECL_SINGLE(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOB3, VPO,
+               SIG_EXPR_PTR(VPOB3, VPO),
+               SIG_EXPR_PTR(VPOB3, VPOOFF1),
+               SIG_EXPR_PTR(VPOB3, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(U19, VPOB3, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(U19, BMCINT, BMCINT, U19_DESC);
+ PIN_DECL_2(U19, GPIOS1, VPOB3, BMCINT);
  FUNC_GROUP_DECL(BMCINT, U19);
  
  #define R18 146
  #define R18_DESC      SIG_DESC_SET(SCU8C, 2)
- SIG_EXPR_DECL(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO),
-               SIG_EXPR_PTR(VPOB4, VPOOFF1), SIG_EXPR_PTR(VPOB4, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(SALT5, SALT5, R18_DESC);
- MS_PIN_DECL(R18, GPIOS2, VPOB4, SALT5);
+ SIG_EXPR_DECL_SINGLE(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOB4, VPO,
+               SIG_EXPR_PTR(VPOB4, VPO),
+               SIG_EXPR_PTR(VPOB4, VPOOFF1),
+               SIG_EXPR_PTR(VPOB4, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(R18, VPOB4, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(R18, SALT5, SALT5, R18_DESC);
+ PIN_DECL_2(R18, GPIOS2, VPOB4, SALT5);
  FUNC_GROUP_DECL(SALT5, R18);
  
  #define P18 147
  #define P18_DESC      SIG_DESC_SET(SCU8C, 3)
- SIG_EXPR_DECL(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO),
-               SIG_EXPR_PTR(VPOB5, VPOOFF1), SIG_EXPR_PTR(VPOB5, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(SALT6, SALT6, P18_DESC);
- MS_PIN_DECL(P18, GPIOS3, VPOB5, SALT6);
+ SIG_EXPR_DECL_SINGLE(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOB5, VPO,
+               SIG_EXPR_PTR(VPOB5, VPO),
+               SIG_EXPR_PTR(VPOB5, VPOOFF1),
+               SIG_EXPR_PTR(VPOB5, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(P18, VPOB5, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(P18, SALT6, SALT6, P18_DESC);
+ PIN_DECL_2(P18, GPIOS3, VPOB5, SALT6);
  FUNC_GROUP_DECL(SALT6, P18);
  
  #define R19 148
  #define R19_DESC      SIG_DESC_SET(SCU8C, 4)
- SIG_EXPR_DECL(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO),
-               SIG_EXPR_PTR(VPOB6, VPOOFF1), SIG_EXPR_PTR(VPOB6, VPOOFF2));
- SS_PIN_DECL(R19, GPIOS4, VPOB6);
+ SIG_EXPR_DECL_SINGLE(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOB6, VPO,
+               SIG_EXPR_PTR(VPOB6, VPO),
+               SIG_EXPR_PTR(VPOB6, VPOOFF1),
+               SIG_EXPR_PTR(VPOB6, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(R19, VPOB6, VPO);
+ PIN_DECL_1(R19, GPIOS4, VPOB6);
  
  #define W20 149
  #define W20_DESC      SIG_DESC_SET(SCU8C, 5)
- SIG_EXPR_DECL(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO),
-               SIG_EXPR_PTR(VPOB7, VPOOFF1), SIG_EXPR_PTR(VPOB7, VPOOFF2));
- SS_PIN_DECL(W20, GPIOS5, VPOB7);
+ SIG_EXPR_DECL_SINGLE(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOB7, VPO,
+               SIG_EXPR_PTR(VPOB7, VPO),
+               SIG_EXPR_PTR(VPOB7, VPOOFF1),
+               SIG_EXPR_PTR(VPOB7, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(W20, VPOB7, VPO);
+ PIN_DECL_1(W20, GPIOS5, VPOB7);
  
  #define U20 150
  #define U20_DESC      SIG_DESC_SET(SCU8C, 6)
- SIG_EXPR_DECL(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOB8, SIG_EXPR_PTR(VPOB8, VPO),
-               SIG_EXPR_PTR(VPOB8, VPOOFF1), SIG_EXPR_PTR(VPOB8, VPOOFF2));
- SS_PIN_DECL(U20, GPIOS6, VPOB8);
+ SIG_EXPR_DECL_SINGLE(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOB8, VPO,
+               SIG_EXPR_PTR(VPOB8, VPO),
+               SIG_EXPR_PTR(VPOB8, VPOOFF1),
+               SIG_EXPR_PTR(VPOB8, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(U20, VPOB8, VPO);
+ PIN_DECL_1(U20, GPIOS6, VPOB8);
  
  #define AA20 151
  #define AA20_DESC     SIG_DESC_SET(SCU8C, 7)
- SIG_EXPR_DECL(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOB9, SIG_EXPR_PTR(VPOB9, VPO),
-               SIG_EXPR_PTR(VPOB9, VPOOFF1), SIG_EXPR_PTR(VPOB9, VPOOFF2));
- SS_PIN_DECL(AA20, GPIOS7, VPOB9);
+ SIG_EXPR_DECL_SINGLE(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOB9, VPO,
+               SIG_EXPR_PTR(VPOB9, VPO),
+               SIG_EXPR_PTR(VPOB9, VPOOFF1),
+               SIG_EXPR_PTR(VPOB9, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(AA20, VPOB9, VPO);
+ PIN_DECL_1(AA20, GPIOS7, VPOB9);
  
  /* RGMII1/RMII1 */
  
@@@ -1098,309 -1137,309 +1137,309 @@@
  #define RMII2_DESC      SIG_DESC_BIT(HW_STRAP1, 7, 0)
  
  #define B5 152
- SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
- SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKO, RMII1, RMII1_DESC,
+ SIG_EXPR_LIST_DECL_SINGLE(B5, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
+ SIG_EXPR_LIST_DECL_SINGLE(B5, RMII1RCLKO, RMII1, RMII1_DESC,
                SIG_DESC_SET(SCU48, 29));
- SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1);
- MS_PIN_DECL_(B5, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1RCLKO),
-               SIG_EXPR_LIST_PTR(RGMII1TXCK));
+ SIG_EXPR_LIST_DECL_SINGLE(B5, RGMII1TXCK, RGMII1);
+ PIN_DECL_(B5, SIG_EXPR_LIST_PTR(B5, GPIOT0), SIG_EXPR_LIST_PTR(B5, RMII1RCLKO),
+               SIG_EXPR_LIST_PTR(B5, RGMII1TXCK));
  
  #define E9 153
- SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
- SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1);
- MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(RMII1TXEN),
-               SIG_EXPR_LIST_PTR(RGMII1TXCTL));
+ SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
+ SIG_EXPR_LIST_DECL_SINGLE(E9, RMII1TXEN, RMII1, RMII1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII1TXCTL, RGMII1);
+ PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT1), SIG_EXPR_LIST_PTR(E9, RMII1TXEN),
+               SIG_EXPR_LIST_PTR(E9, RGMII1TXCTL));
  
  #define F9 154
- SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
- SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1);
- MS_PIN_DECL_(F9, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0),
-               SIG_EXPR_LIST_PTR(RGMII1TXD0));
+ SIG_EXPR_LIST_DECL_SINGLE(F9, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
+ SIG_EXPR_LIST_DECL_SINGLE(F9, RMII1TXD0, RMII1, RMII1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(F9, RGMII1TXD0, RGMII1);
+ PIN_DECL_(F9, SIG_EXPR_LIST_PTR(F9, GPIOT2), SIG_EXPR_LIST_PTR(F9, RMII1TXD0),
+               SIG_EXPR_LIST_PTR(F9, RGMII1TXD0));
  
  #define A5 155
- SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
- SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1);
- MS_PIN_DECL_(A5, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1),
-               SIG_EXPR_LIST_PTR(RGMII1TXD1));
+ SIG_EXPR_LIST_DECL_SINGLE(A5, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
+ SIG_EXPR_LIST_DECL_SINGLE(A5, RMII1TXD1, RMII1, RMII1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(A5, RGMII1TXD1, RGMII1);
+ PIN_DECL_(A5, SIG_EXPR_LIST_PTR(A5, GPIOT3), SIG_EXPR_LIST_PTR(A5, RMII1TXD1),
+               SIG_EXPR_LIST_PTR(A5, RGMII1TXD1));
  
  #define E7 156
- SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
- SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH0, RMII1, RMII1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1);
- MS_PIN_DECL_(E7, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(RMII1DASH0),
-               SIG_EXPR_LIST_PTR(RGMII1TXD2));
+ SIG_EXPR_LIST_DECL_SINGLE(E7, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
+ SIG_EXPR_LIST_DECL_SINGLE(E7, RMII1DASH0, RMII1, RMII1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(E7, RGMII1TXD2, RGMII1);
+ PIN_DECL_(E7, SIG_EXPR_LIST_PTR(E7, GPIOT4), SIG_EXPR_LIST_PTR(E7, RMII1DASH0),
+               SIG_EXPR_LIST_PTR(E7, RGMII1TXD2));
  
  #define D7 157
- SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
- SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH1, RMII1, RMII1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1);
- MS_PIN_DECL_(D7, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(RMII1DASH1),
-               SIG_EXPR_LIST_PTR(RGMII1TXD3));
+ SIG_EXPR_LIST_DECL_SINGLE(D7, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
+ SIG_EXPR_LIST_DECL_SINGLE(D7, RMII1DASH1, RMII1, RMII1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(D7, RGMII1TXD3, RGMII1);
+ PIN_DECL_(D7, SIG_EXPR_LIST_PTR(D7, GPIOT5), SIG_EXPR_LIST_PTR(D7, RMII1DASH1),
+               SIG_EXPR_LIST_PTR(D7, RGMII1TXD3));
  
  #define B2 158
- SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
- SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKO, RMII2, RMII2_DESC,
+ SIG_EXPR_LIST_DECL_SINGLE(B2, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
+ SIG_EXPR_LIST_DECL_SINGLE(B2, RMII2RCLKO, RMII2, RMII2_DESC,
                SIG_DESC_SET(SCU48, 30));
- SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2);
- MS_PIN_DECL_(B2, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2RCLKO),
-               SIG_EXPR_LIST_PTR(RGMII2TXCK));
+ SIG_EXPR_LIST_DECL_SINGLE(B2, RGMII2TXCK, RGMII2);
+ PIN_DECL_(B2, SIG_EXPR_LIST_PTR(B2, GPIOT6), SIG_EXPR_LIST_PTR(B2, RMII2RCLKO),
+               SIG_EXPR_LIST_PTR(B2, RGMII2TXCK));
  
  #define B1 159
- SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
- SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2);
- MS_PIN_DECL_(B1, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(RMII2TXEN),
-               SIG_EXPR_LIST_PTR(RGMII2TXCTL));
+ SIG_EXPR_LIST_DECL_SINGLE(B1, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
+ SIG_EXPR_LIST_DECL_SINGLE(B1, RMII2TXEN, RMII2, RMII2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(B1, RGMII2TXCTL, RGMII2);
+ PIN_DECL_(B1, SIG_EXPR_LIST_PTR(B1, GPIOT7), SIG_EXPR_LIST_PTR(B1, RMII2TXEN),
+               SIG_EXPR_LIST_PTR(B1, RGMII2TXCTL));
  
  #define A2 160
- SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
- SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2);
- MS_PIN_DECL_(A2, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0),
-               SIG_EXPR_LIST_PTR(RGMII2TXD0));
+ SIG_EXPR_LIST_DECL_SINGLE(A2, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
+ SIG_EXPR_LIST_DECL_SINGLE(A2, RMII2TXD0, RMII2, RMII2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(A2, RGMII2TXD0, RGMII2);
+ PIN_DECL_(A2, SIG_EXPR_LIST_PTR(A2, GPIOU0), SIG_EXPR_LIST_PTR(A2, RMII2TXD0),
+               SIG_EXPR_LIST_PTR(A2, RGMII2TXD0));
  
  #define B3 161
- SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
- SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2);
- MS_PIN_DECL_(B3, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1),
-               SIG_EXPR_LIST_PTR(RGMII2TXD1));
+ SIG_EXPR_LIST_DECL_SINGLE(B3, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
+ SIG_EXPR_LIST_DECL_SINGLE(B3, RMII2TXD1, RMII2, RMII2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(B3, RGMII2TXD1, RGMII2);
+ PIN_DECL_(B3, SIG_EXPR_LIST_PTR(B3, GPIOU1), SIG_EXPR_LIST_PTR(B3, RMII2TXD1),
+               SIG_EXPR_LIST_PTR(B3, RGMII2TXD1));
  
  #define D5 162
- SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
- SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH0, RMII2, RMII2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2);
- MS_PIN_DECL_(D5, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(RMII2DASH0),
-               SIG_EXPR_LIST_PTR(RGMII2TXD2));
+ SIG_EXPR_LIST_DECL_SINGLE(D5, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
+ SIG_EXPR_LIST_DECL_SINGLE(D5, RMII2DASH0, RMII2, RMII2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(D5, RGMII2TXD2, RGMII2);
+ PIN_DECL_(D5, SIG_EXPR_LIST_PTR(D5, GPIOU2), SIG_EXPR_LIST_PTR(D5, RMII2DASH0),
+               SIG_EXPR_LIST_PTR(D5, RGMII2TXD2));
  
  #define D4 163
- SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
- SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH1, RMII2, RMII2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2);
- MS_PIN_DECL_(D4, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(RMII2DASH1),
-               SIG_EXPR_LIST_PTR(RGMII2TXD3));
+ SIG_EXPR_LIST_DECL_SINGLE(D4, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
+ SIG_EXPR_LIST_DECL_SINGLE(D4, RMII2DASH1, RMII2, RMII2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(D4, RGMII2TXD3, RGMII2);
+ PIN_DECL_(D4, SIG_EXPR_LIST_PTR(D4, GPIOU3), SIG_EXPR_LIST_PTR(D4, RMII2DASH1),
+               SIG_EXPR_LIST_PTR(D4, RGMII2TXD3));
  
  #define B4 164
- SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
- SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKI, RMII1, RMII1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1);
- MS_PIN_DECL_(B4, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLKI),
-               SIG_EXPR_LIST_PTR(RGMII1RXCK));
+ SIG_EXPR_LIST_DECL_SINGLE(B4, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
+ SIG_EXPR_LIST_DECL_SINGLE(B4, RMII1RCLKI, RMII1, RMII1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(B4, RGMII1RXCK, RGMII1);
+ PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, GPIOU4), SIG_EXPR_LIST_PTR(B4, RMII1RCLKI),
+               SIG_EXPR_LIST_PTR(B4, RGMII1RXCK));
  
  #define A4 165
- SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
- SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH2, RMII1, RMII1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1);
- MS_PIN_DECL_(A4, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(RMII1DASH2),
-               SIG_EXPR_LIST_PTR(RGMII1RXCTL));
+ SIG_EXPR_LIST_DECL_SINGLE(A4, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
+ SIG_EXPR_LIST_DECL_SINGLE(A4, RMII1DASH2, RMII1, RMII1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(A4, RGMII1RXCTL, RGMII1);
+ PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, GPIOU5), SIG_EXPR_LIST_PTR(A4, RMII1DASH2),
+               SIG_EXPR_LIST_PTR(A4, RGMII1RXCTL));
  
  #define A3 166
- SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
- SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1);
- MS_PIN_DECL_(A3, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0),
-               SIG_EXPR_LIST_PTR(RGMII1RXD0));
+ SIG_EXPR_LIST_DECL_SINGLE(A3, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
+ SIG_EXPR_LIST_DECL_SINGLE(A3, RMII1RXD0, RMII1, RMII1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(A3, RGMII1RXD0, RGMII1);
+ PIN_DECL_(A3, SIG_EXPR_LIST_PTR(A3, GPIOU6), SIG_EXPR_LIST_PTR(A3, RMII1RXD0),
+               SIG_EXPR_LIST_PTR(A3, RGMII1RXD0));
  
  #define D6 167
- SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
- SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1);
- MS_PIN_DECL_(D6, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1),
-               SIG_EXPR_LIST_PTR(RGMII1RXD1));
+ SIG_EXPR_LIST_DECL_SINGLE(D6, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
+ SIG_EXPR_LIST_DECL_SINGLE(D6, RMII1RXD1, RMII1, RMII1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(D6, RGMII1RXD1, RGMII1);
+ PIN_DECL_(D6, SIG_EXPR_LIST_PTR(D6, GPIOU7), SIG_EXPR_LIST_PTR(D6, RMII1RXD1),
+               SIG_EXPR_LIST_PTR(D6, RGMII1RXD1));
  
  #define C5 168
- SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
- SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1);
- MS_PIN_DECL_(C5, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV),
-               SIG_EXPR_LIST_PTR(RGMII1RXD2));
+ SIG_EXPR_LIST_DECL_SINGLE(C5, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
+ SIG_EXPR_LIST_DECL_SINGLE(C5, RMII1CRSDV, RMII1, RMII1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(C5, RGMII1RXD2, RGMII1);
+ PIN_DECL_(C5, SIG_EXPR_LIST_PTR(C5, GPIOV0), SIG_EXPR_LIST_PTR(C5, RMII1CRSDV),
+               SIG_EXPR_LIST_PTR(C5, RGMII1RXD2));
  
  #define C4 169
- SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
- SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1);
- MS_PIN_DECL_(C4, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER),
-               SIG_EXPR_LIST_PTR(RGMII1RXD3));
+ SIG_EXPR_LIST_DECL_SINGLE(C4, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
+ SIG_EXPR_LIST_DECL_SINGLE(C4, RMII1RXER, RMII1, RMII1_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(C4, RGMII1RXD3, RGMII1);
+ PIN_DECL_(C4, SIG_EXPR_LIST_PTR(C4, GPIOV1), SIG_EXPR_LIST_PTR(C4, RMII1RXER),
+               SIG_EXPR_LIST_PTR(C4, RGMII1RXD3));
  
  FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7);
  FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5);
  
  #define C2 170
- SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
- SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKI, RMII2, RMII2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2);
- MS_PIN_DECL_(C2, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLKI),
-               SIG_EXPR_LIST_PTR(RGMII2RXCK));
+ SIG_EXPR_LIST_DECL_SINGLE(C2, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
+ SIG_EXPR_LIST_DECL_SINGLE(C2, RMII2RCLKI, RMII2, RMII2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(C2, RGMII2RXCK, RGMII2);
+ PIN_DECL_(C2, SIG_EXPR_LIST_PTR(C2, GPIOV2), SIG_EXPR_LIST_PTR(C2, RMII2RCLKI),
+               SIG_EXPR_LIST_PTR(C2, RGMII2RXCK));
  
  #define C1 171
- SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
- SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH2, RMII2, RMII2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2);
- MS_PIN_DECL_(C1, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(RMII2DASH2),
-               SIG_EXPR_LIST_PTR(RGMII2RXCTL));
+ SIG_EXPR_LIST_DECL_SINGLE(C1, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
+ SIG_EXPR_LIST_DECL_SINGLE(C1, RMII2DASH2, RMII2, RMII2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(C1, RGMII2RXCTL, RGMII2);
+ PIN_DECL_(C1, SIG_EXPR_LIST_PTR(C1, GPIOV3), SIG_EXPR_LIST_PTR(C1, RMII2DASH2),
+               SIG_EXPR_LIST_PTR(C1, RGMII2RXCTL));
  
  #define C3 172
- SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
- SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2);
- MS_PIN_DECL_(C3, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0),
-               SIG_EXPR_LIST_PTR(RGMII2RXD0));
+ SIG_EXPR_LIST_DECL_SINGLE(C3, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
+ SIG_EXPR_LIST_DECL_SINGLE(C3, RMII2RXD0, RMII2, RMII2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(C3, RGMII2RXD0, RGMII2);
+ PIN_DECL_(C3, SIG_EXPR_LIST_PTR(C3, GPIOV4), SIG_EXPR_LIST_PTR(C3, RMII2RXD0),
+               SIG_EXPR_LIST_PTR(C3, RGMII2RXD0));
  
  #define D1 173
- SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
- SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2);
- MS_PIN_DECL_(D1, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1),
-               SIG_EXPR_LIST_PTR(RGMII2RXD1));
+ SIG_EXPR_LIST_DECL_SINGLE(D1, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
+ SIG_EXPR_LIST_DECL_SINGLE(D1, RMII2RXD1, RMII2, RMII2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(D1, RGMII2RXD1, RGMII2);
+ PIN_DECL_(D1, SIG_EXPR_LIST_PTR(D1, GPIOV5), SIG_EXPR_LIST_PTR(D1, RMII2RXD1),
+               SIG_EXPR_LIST_PTR(D1, RGMII2RXD1));
  
  #define D2 174
- SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
- SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2);
- MS_PIN_DECL_(D2, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV),
-               SIG_EXPR_LIST_PTR(RGMII2RXD2));
+ SIG_EXPR_LIST_DECL_SINGLE(D2, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
+ SIG_EXPR_LIST_DECL_SINGLE(D2, RMII2CRSDV, RMII2, RMII2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(D2, RGMII2RXD2, RGMII2);
+ PIN_DECL_(D2, SIG_EXPR_LIST_PTR(D2, GPIOV6), SIG_EXPR_LIST_PTR(D2, RMII2CRSDV),
+               SIG_EXPR_LIST_PTR(D2, RGMII2RXD2));
  
  #define E6 175
- SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
- SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2);
- MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER),
-               SIG_EXPR_LIST_PTR(RGMII2RXD3));
+ SIG_EXPR_LIST_DECL_SINGLE(E6, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
+ SIG_EXPR_LIST_DECL_SINGLE(E6, RMII2RXER, RMII2, RMII2_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(E6, RGMII2RXD3, RGMII2);
+ PIN_DECL_(E6, SIG_EXPR_LIST_PTR(E6, GPIOV7), SIG_EXPR_LIST_PTR(E6, RMII2RXER),
+               SIG_EXPR_LIST_PTR(E6, RGMII2RXD3));
  
  FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
  FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
  
  #define F4 176
- SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
- SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0);
- MS_PIN_DECL_(F4, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0));
+ SIG_EXPR_LIST_DECL_SINGLE(F4, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
+ SIG_EXPR_LIST_DECL_SINGLE(F4, ADC0, ADC0);
+ PIN_DECL_(F4, SIG_EXPR_LIST_PTR(F4, GPIOW0), SIG_EXPR_LIST_PTR(F4, ADC0));
  FUNC_GROUP_DECL(ADC0, F4);
  
  #define F5 177
- SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
- SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1);
- MS_PIN_DECL_(F5, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1));
+ SIG_EXPR_LIST_DECL_SINGLE(F5, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
+ SIG_EXPR_LIST_DECL_SINGLE(F5, ADC1, ADC1);
+ PIN_DECL_(F5, SIG_EXPR_LIST_PTR(F5, GPIOW1), SIG_EXPR_LIST_PTR(F5, ADC1));
  FUNC_GROUP_DECL(ADC1, F5);
  
  #define E2 178
- SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
- SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2);
- MS_PIN_DECL_(E2, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2));
+ SIG_EXPR_LIST_DECL_SINGLE(E2, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
+ SIG_EXPR_LIST_DECL_SINGLE(E2, ADC2, ADC2);
+ PIN_DECL_(E2, SIG_EXPR_LIST_PTR(E2, GPIOW2), SIG_EXPR_LIST_PTR(E2, ADC2));
  FUNC_GROUP_DECL(ADC2, E2);
  
  #define E1 179
- SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
- SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3);
- MS_PIN_DECL_(E1, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3));
+ SIG_EXPR_LIST_DECL_SINGLE(E1, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
+ SIG_EXPR_LIST_DECL_SINGLE(E1, ADC3, ADC3);
+ PIN_DECL_(E1, SIG_EXPR_LIST_PTR(E1, GPIOW3), SIG_EXPR_LIST_PTR(E1, ADC3));
  FUNC_GROUP_DECL(ADC3, E1);
  
  #define F3 180
- SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
- SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4);
- MS_PIN_DECL_(F3, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4));
+ SIG_EXPR_LIST_DECL_SINGLE(F3, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
+ SIG_EXPR_LIST_DECL_SINGLE(F3, ADC4, ADC4);
+ PIN_DECL_(F3, SIG_EXPR_LIST_PTR(F3, GPIOW4), SIG_EXPR_LIST_PTR(F3, ADC4));
  FUNC_GROUP_DECL(ADC4, F3);
  
  #define E3 181
- SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
- SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5);
- MS_PIN_DECL_(E3, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5));
+ SIG_EXPR_LIST_DECL_SINGLE(E3, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
+ SIG_EXPR_LIST_DECL_SINGLE(E3, ADC5, ADC5);
+ PIN_DECL_(E3, SIG_EXPR_LIST_PTR(E3, GPIOW5), SIG_EXPR_LIST_PTR(E3, ADC5));
  FUNC_GROUP_DECL(ADC5, E3);
  
  #define G5 182
- SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
- SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6);
- MS_PIN_DECL_(G5, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6));
+ SIG_EXPR_LIST_DECL_SINGLE(G5, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
+ SIG_EXPR_LIST_DECL_SINGLE(G5, ADC6, ADC6);
+ PIN_DECL_(G5, SIG_EXPR_LIST_PTR(G5, GPIOW6), SIG_EXPR_LIST_PTR(G5, ADC6));
  FUNC_GROUP_DECL(ADC6, G5);
  
  #define G4 183
- SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
- SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7);
- MS_PIN_DECL_(G4, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7));
+ SIG_EXPR_LIST_DECL_SINGLE(G4, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
+ SIG_EXPR_LIST_DECL_SINGLE(G4, ADC7, ADC7);
+ PIN_DECL_(G4, SIG_EXPR_LIST_PTR(G4, GPIOW7), SIG_EXPR_LIST_PTR(G4, ADC7));
  FUNC_GROUP_DECL(ADC7, G4);
  
  #define F2 184
- SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
- SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8);
- MS_PIN_DECL_(F2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8));
+ SIG_EXPR_LIST_DECL_SINGLE(F2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
+ SIG_EXPR_LIST_DECL_SINGLE(F2, ADC8, ADC8);
+ PIN_DECL_(F2, SIG_EXPR_LIST_PTR(F2, GPIOX0), SIG_EXPR_LIST_PTR(F2, ADC8));
  FUNC_GROUP_DECL(ADC8, F2);
  
  #define G3 185
- SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
- SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9);
- MS_PIN_DECL_(G3, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9));
+ SIG_EXPR_LIST_DECL_SINGLE(G3, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
+ SIG_EXPR_LIST_DECL_SINGLE(G3, ADC9, ADC9);
+ PIN_DECL_(G3, SIG_EXPR_LIST_PTR(G3, GPIOX1), SIG_EXPR_LIST_PTR(G3, ADC9));
  FUNC_GROUP_DECL(ADC9, G3);
  
  #define G2 186
- SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
- SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10);
- MS_PIN_DECL_(G2, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10));
+ SIG_EXPR_LIST_DECL_SINGLE(G2, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
+ SIG_EXPR_LIST_DECL_SINGLE(G2, ADC10, ADC10);
+ PIN_DECL_(G2, SIG_EXPR_LIST_PTR(G2, GPIOX2), SIG_EXPR_LIST_PTR(G2, ADC10));
  FUNC_GROUP_DECL(ADC10, G2);
  
  #define F1 187
- SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
- SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11);
- MS_PIN_DECL_(F1, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11));
+ SIG_EXPR_LIST_DECL_SINGLE(F1, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
+ SIG_EXPR_LIST_DECL_SINGLE(F1, ADC11, ADC11);
+ PIN_DECL_(F1, SIG_EXPR_LIST_PTR(F1, GPIOX3), SIG_EXPR_LIST_PTR(F1, ADC11));
  FUNC_GROUP_DECL(ADC11, F1);
  
  #define H5 188
- SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
- SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12);
- MS_PIN_DECL_(H5, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12));
+ SIG_EXPR_LIST_DECL_SINGLE(H5, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
+ SIG_EXPR_LIST_DECL_SINGLE(H5, ADC12, ADC12);
+ PIN_DECL_(H5, SIG_EXPR_LIST_PTR(H5, GPIOX4), SIG_EXPR_LIST_PTR(H5, ADC12));
  FUNC_GROUP_DECL(ADC12, H5);
  
  #define G1 189
- SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
- SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13);
- MS_PIN_DECL_(G1, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13));
+ SIG_EXPR_LIST_DECL_SINGLE(G1, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
+ SIG_EXPR_LIST_DECL_SINGLE(G1, ADC13, ADC13);
+ PIN_DECL_(G1, SIG_EXPR_LIST_PTR(G1, GPIOX5), SIG_EXPR_LIST_PTR(G1, ADC13));
  FUNC_GROUP_DECL(ADC13, G1);
  
  #define H3 190
- SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
- SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14);
- MS_PIN_DECL_(H3, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14));
+ SIG_EXPR_LIST_DECL_SINGLE(H3, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
+ SIG_EXPR_LIST_DECL_SINGLE(H3, ADC14, ADC14);
+ PIN_DECL_(H3, SIG_EXPR_LIST_PTR(H3, GPIOX6), SIG_EXPR_LIST_PTR(H3, ADC14));
  FUNC_GROUP_DECL(ADC14, H3);
  
  #define H4 191
- SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
- SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15);
- MS_PIN_DECL_(H4, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15));
+ SIG_EXPR_LIST_DECL_SINGLE(H4, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
+ SIG_EXPR_LIST_DECL_SINGLE(H4, ADC15, ADC15);
+ PIN_DECL_(H4, SIG_EXPR_LIST_PTR(H4, GPIOX7), SIG_EXPR_LIST_PTR(H4, ADC15));
  FUNC_GROUP_DECL(ADC15, H4);
  
  #define ACPI_DESC     SIG_DESC_SET(HW_STRAP1, 19)
  
  #define R22 192
- SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
- SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC);
- SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI);
- SIG_EXPR_LIST_DECL_SINGLE(DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10));
- MS_PIN_DECL(R22, GPIOY0, SIOS3, DASHR22);
+ SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
+ SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(R22, SIOS3, SIOS3, ACPI);
+ SIG_EXPR_LIST_DECL_SINGLE(R22, DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10));
+ PIN_DECL_2(R22, GPIOY0, SIOS3, DASHR22);
  FUNC_GROUP_DECL(SIOS3, R22);
  
  #define R21 193
- SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
- SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC);
- SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI);
- SIG_EXPR_LIST_DECL_SINGLE(DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10));
- MS_PIN_DECL(R21, GPIOY1, SIOS5, DASHR21);
+ SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
+ SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(R21, SIOS5, SIOS5, ACPI);
+ SIG_EXPR_LIST_DECL_SINGLE(R21, DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10));
+ PIN_DECL_2(R21, GPIOY1, SIOS5, DASHR21);
  FUNC_GROUP_DECL(SIOS5, R21);
  
  #define P22 194
- SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
- SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC);
- SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI);
- SIG_EXPR_LIST_DECL_SINGLE(DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11));
- MS_PIN_DECL(P22, GPIOY2, SIOPWREQ, DASHP22);
+ SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
+ SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(P22, SIOPWREQ, SIOPWREQ, ACPI);
+ SIG_EXPR_LIST_DECL_SINGLE(P22, DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11));
+ PIN_DECL_2(P22, GPIOY2, SIOPWREQ, DASHP22);
  FUNC_GROUP_DECL(SIOPWREQ, P22);
  
  #define P21 195
- SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
- SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC);
- SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI);
- SIG_EXPR_LIST_DECL_SINGLE(DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11));
- MS_PIN_DECL(P21, GPIOY3, SIOONCTRL, DASHP21);
+ SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
+ SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(P21, SIOONCTRL, SIOONCTRL, ACPI);
+ SIG_EXPR_LIST_DECL_SINGLE(P21, DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11));
+ PIN_DECL_2(P21, GPIOY3, SIOONCTRL, DASHP21);
  FUNC_GROUP_DECL(SIOONCTRL, P21);
  
  #define M18 196
@@@ -1419,66 -1458,81 +1458,81 @@@ SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DE
  
  #define Y20 200
  #define Y20_DESC      SIG_DESC_SET(SCUA4, 16)
- SIG_EXPR_DECL(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO),
-               SIG_EXPR_PTR(VPOG2, VPOOFF1), SIG_EXPR_PTR(VPOG2, VPOOFF2));
- SIG_EXPR_DECL(SIOPBI, SIOPBI, Y20_DESC);
- SIG_EXPR_DECL(SIOPBI, ACPI, Y20_DESC);
- SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI);
- SIG_EXPR_LIST_DECL_SINGLE(NORA0, PNOR, PNOR_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(GPIOZ0, GPIOZ0);
- MS_PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(VPOG2), SIG_EXPR_LIST_PTR(SIOPBI),
-               SIG_EXPR_LIST_PTR(NORA0), SIG_EXPR_LIST_PTR(GPIOZ0));
+ SIG_EXPR_DECL_SINGLE(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOG2, VPO,
+               SIG_EXPR_PTR(VPOG2, VPO),
+               SIG_EXPR_PTR(VPOG2, VPOOFF1),
+               SIG_EXPR_PTR(VPOG2, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(Y20, VPOG2, VPO);
+ SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, Y20_DESC);
+ SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, Y20_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(Y20, SIOPBI, SIOPBI, ACPI);
+ SIG_EXPR_LIST_DECL_SINGLE(Y20, NORA0, PNOR, PNOR_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(Y20, GPIOZ0, GPIOZ0);
+ PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(Y20, VPOG2), SIG_EXPR_LIST_PTR(Y20, SIOPBI),
+               SIG_EXPR_LIST_PTR(Y20, NORA0), SIG_EXPR_LIST_PTR(Y20, GPIOZ0));
  FUNC_GROUP_DECL(SIOPBI, Y20);
  
  #define AB20 201
  #define AB20_DESC     SIG_DESC_SET(SCUA4, 17)
- SIG_EXPR_DECL(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO),
-               SIG_EXPR_PTR(VPOG3, VPOOFF1), SIG_EXPR_PTR(VPOG3, VPOOFF2));
- SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, AB20_DESC);
- SIG_EXPR_DECL(SIOPWRGD, ACPI, AB20_DESC);
- SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI);
- SIG_EXPR_LIST_DECL_SINGLE(NORA1, PNOR, PNOR_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(GPIOZ1, GPIOZ1);
- MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(VPOG3), SIG_EXPR_LIST_PTR(SIOPWRGD),
-               SIG_EXPR_LIST_PTR(NORA1), SIG_EXPR_LIST_PTR(GPIOZ1));
+ SIG_EXPR_DECL_SINGLE(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOG3, VPO,
+               SIG_EXPR_PTR(VPOG3, VPO),
+               SIG_EXPR_PTR(VPOG3, VPOOFF1),
+               SIG_EXPR_PTR(VPOG3, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(AB20, VPOG3, VPO);
+ SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, AB20_DESC);
+ SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, AB20_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(AB20, SIOPWRGD, SIOPWRGD, ACPI);
+ SIG_EXPR_LIST_DECL_SINGLE(AB20, NORA1, PNOR, PNOR_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(AB20, GPIOZ1, GPIOZ1);
+ PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, VPOG3),
+         SIG_EXPR_LIST_PTR(AB20, SIOPWRGD), SIG_EXPR_LIST_PTR(AB20, NORA1),
+         SIG_EXPR_LIST_PTR(AB20, GPIOZ1));
  FUNC_GROUP_DECL(SIOPWRGD, AB20);
  
  #define AB21 202
  #define AB21_DESC     SIG_DESC_SET(SCUA4, 18)
- SIG_EXPR_DECL(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOG4, SIG_EXPR_PTR(VPOG4, VPO),
-               SIG_EXPR_PTR(VPOG4, VPOOFF1), SIG_EXPR_PTR(VPOG4, VPOOFF2));
- SIG_EXPR_DECL(SIOPBO, SIOPBO, AB21_DESC);
- SIG_EXPR_DECL(SIOPBO, ACPI, AB21_DESC);
- SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI);
- SIG_EXPR_LIST_DECL_SINGLE(NORA2, PNOR, PNOR_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(GPIOZ2, GPIOZ2);
- MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(VPOG4), SIG_EXPR_LIST_PTR(SIOPBO),
-               SIG_EXPR_LIST_PTR(NORA2), SIG_EXPR_LIST_PTR(GPIOZ2));
+ SIG_EXPR_DECL_SINGLE(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOG4, VPO,
+               SIG_EXPR_PTR(VPOG4, VPO),
+               SIG_EXPR_PTR(VPOG4, VPOOFF1),
+               SIG_EXPR_PTR(VPOG4, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(AB21, VPOG4, VPO);
+ SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, AB21_DESC);
+ SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, AB21_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(AB21, SIOPBO, SIOPBO, ACPI);
+ SIG_EXPR_LIST_DECL_SINGLE(AB21, NORA2, PNOR, PNOR_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(AB21, GPIOZ2, GPIOZ2);
+ PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, VPOG4),
+         SIG_EXPR_LIST_PTR(AB21, SIOPBO), SIG_EXPR_LIST_PTR(AB21, NORA2),
+         SIG_EXPR_LIST_PTR(AB21, GPIOZ2));
  FUNC_GROUP_DECL(SIOPBO, AB21);
  
  #define AA21 203
  #define AA21_DESC     SIG_DESC_SET(SCUA4, 19)
- SIG_EXPR_DECL(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOG5, SIG_EXPR_PTR(VPOG5, VPO),
-               SIG_EXPR_PTR(VPOG5, VPOOFF1), SIG_EXPR_PTR(VPOG5, VPOOFF2));
- SIG_EXPR_DECL(SIOSCI, SIOSCI, AA21_DESC);
- SIG_EXPR_DECL(SIOSCI, ACPI, AA21_DESC);
- SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI);
- SIG_EXPR_LIST_DECL_SINGLE(NORA3, PNOR, PNOR_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(GPIOZ3, GPIOZ3);
- MS_PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(VPOG5), SIG_EXPR_LIST_PTR(SIOSCI),
-               SIG_EXPR_LIST_PTR(NORA3), SIG_EXPR_LIST_PTR(GPIOZ3));
+ SIG_EXPR_DECL_SINGLE(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOG5, VPO,
+               SIG_EXPR_PTR(VPOG5, VPO),
+               SIG_EXPR_PTR(VPOG5, VPOOFF1),
+               SIG_EXPR_PTR(VPOG5, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(AA21, VPOG5, VPO);
+ SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, AA21_DESC);
+ SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, AA21_DESC);
+ SIG_EXPR_LIST_DECL_DUAL(AA21, SIOSCI, SIOSCI, ACPI);
+ SIG_EXPR_LIST_DECL_SINGLE(AA21, NORA3, PNOR, PNOR_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(AA21, GPIOZ3, GPIOZ3);
+ PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(AA21, VPOG5),
+         SIG_EXPR_LIST_PTR(AA21, SIOSCI), SIG_EXPR_LIST_PTR(AA21, NORA3),
+         SIG_EXPR_LIST_PTR(AA21, GPIOZ3));
  FUNC_GROUP_DECL(SIOSCI, AA21);
  
  FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21);
@@@ -1497,199 -1551,248 +1551,248 @@@
  
  #define U21 204
  #define U21_DESC      SIG_DESC_SET(SCUA4, 20)
- SIG_EXPR_DECL(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_LIST_DECL(VPOG6, SIG_EXPR_PTR(VPOG6, VPO),
-               SIG_EXPR_PTR(VPOG6, VPOOFF1), SIG_EXPR_PTR(VPOG6, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(NORA4, PNOR, PNOR_DESC);
- MS_PIN_DECL(U21, GPIOZ4, VPOG6, NORA4);
+ SIG_EXPR_DECL_SINGLE(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_LIST_DECL(VPOG6, VPO,
+               SIG_EXPR_PTR(VPOG6, VPO),
+               SIG_EXPR_PTR(VPOG6, VPOOFF1),
+               SIG_EXPR_PTR(VPOG6, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(U21, VPOG6, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(U21, NORA4, PNOR, PNOR_DESC);
+ PIN_DECL_2(U21, GPIOZ4, VPOG6, NORA4);
  
  #define W22 205
  #define W22_DESC      SIG_DESC_SET(SCUA4, 21)
- SIG_EXPR_DECL(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_LIST_DECL(VPOG7, SIG_EXPR_PTR(VPOG7, VPO),
-               SIG_EXPR_PTR(VPOG7, VPOOFF1), SIG_EXPR_PTR(VPOG7, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(NORA5, PNOR, PNOR_DESC);
- MS_PIN_DECL(W22, GPIOZ5, VPOG7, NORA5);
+ SIG_EXPR_DECL_SINGLE(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_LIST_DECL(VPOG7, VPO,
+               SIG_EXPR_PTR(VPOG7, VPO),
+               SIG_EXPR_PTR(VPOG7, VPOOFF1),
+               SIG_EXPR_PTR(VPOG7, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(W22, VPOG7, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(W22, NORA5, PNOR, PNOR_DESC);
+ PIN_DECL_2(W22, GPIOZ5, VPOG7, NORA5);
  
  #define V22 206
  #define V22_DESC      SIG_DESC_SET(SCUA4, 22)
- SIG_EXPR_DECL(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_LIST_DECL(VPOG8, SIG_EXPR_PTR(VPOG8, VPO),
-               SIG_EXPR_PTR(VPOG8, VPOOFF1), SIG_EXPR_PTR(VPOG8, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(NORA6, PNOR, PNOR_DESC);
- MS_PIN_DECL(V22, GPIOZ6, VPOG8, NORA6);
+ SIG_EXPR_DECL_SINGLE(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_LIST_DECL(VPOG8, VPO,
+               SIG_EXPR_PTR(VPOG8, VPO),
+               SIG_EXPR_PTR(VPOG8, VPOOFF1),
+               SIG_EXPR_PTR(VPOG8, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(V22, VPOG8, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(V22, NORA6, PNOR, PNOR_DESC);
+ PIN_DECL_2(V22, GPIOZ6, VPOG8, NORA6);
  
  #define W21 207
  #define W21_DESC      SIG_DESC_SET(SCUA4, 23)
- SIG_EXPR_DECL(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_LIST_DECL(VPOG9, SIG_EXPR_PTR(VPOG9, VPO),
-               SIG_EXPR_PTR(VPOG9, VPOOFF1), SIG_EXPR_PTR(VPOG9, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(NORA7, PNOR, PNOR_DESC);
- MS_PIN_DECL(W21, GPIOZ7, VPOG9, NORA7);
+ SIG_EXPR_DECL_SINGLE(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_LIST_DECL(VPOG9, VPO,
+               SIG_EXPR_PTR(VPOG9, VPO),
+               SIG_EXPR_PTR(VPOG9, VPOOFF1),
+               SIG_EXPR_PTR(VPOG9, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(W21, VPOG9, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(W21, NORA7, PNOR, PNOR_DESC);
+ PIN_DECL_2(W21, GPIOZ7, VPOG9, NORA7);
  
  #define Y21 208
  #define Y21_DESC      SIG_DESC_SET(SCUA4, 24)
- SIG_EXPR_DECL(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_LIST_DECL(VPOR2, SIG_EXPR_PTR(VPOR2, VPO),
-               SIG_EXPR_PTR(VPOR2, VPOOFF1), SIG_EXPR_PTR(VPOR2, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(SALT7, SALT7, Y21_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(NORD0, PNOR, PNOR_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(GPIOAA0, GPIOAA0);
- MS_PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(VPOR2), SIG_EXPR_LIST_PTR(SALT7),
-               SIG_EXPR_LIST_PTR(NORD0), SIG_EXPR_LIST_PTR(GPIOAA0));
+ SIG_EXPR_DECL_SINGLE(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_LIST_DECL(VPOR2, VPO,
+               SIG_EXPR_PTR(VPOR2, VPO),
+               SIG_EXPR_PTR(VPOR2, VPOOFF1),
+               SIG_EXPR_PTR(VPOR2, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(Y21, VPOR2, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(Y21, SALT7, SALT7, Y21_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(Y21, NORD0, PNOR, PNOR_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(Y21, GPIOAA0, GPIOAA0);
+ PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(Y21, VPOR2), SIG_EXPR_LIST_PTR(Y21, SALT7),
+               SIG_EXPR_LIST_PTR(Y21, NORD0), SIG_EXPR_LIST_PTR(Y21, GPIOAA0));
  FUNC_GROUP_DECL(SALT7, Y21);
  
  #define V21 209
  #define V21_DESC      SIG_DESC_SET(SCUA4, 25)
- SIG_EXPR_DECL(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_LIST_DECL(VPOR3, SIG_EXPR_PTR(VPOR3, VPO),
-               SIG_EXPR_PTR(VPOR3, VPOOFF1), SIG_EXPR_PTR(VPOR3, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(SALT8, SALT8, V21_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(NORD1, PNOR, PNOR_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(GPIOAA1, GPIOAA1);
- MS_PIN_DECL_(V21, SIG_EXPR_LIST_PTR(VPOR3), SIG_EXPR_LIST_PTR(SALT8),
-               SIG_EXPR_LIST_PTR(NORD1), SIG_EXPR_LIST_PTR(GPIOAA1));
+ SIG_EXPR_DECL_SINGLE(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_LIST_DECL(VPOR3, VPO,
+               SIG_EXPR_PTR(VPOR3, VPO),
+               SIG_EXPR_PTR(VPOR3, VPOOFF1),
+               SIG_EXPR_PTR(VPOR3, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(V21, VPOR3, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(V21, SALT8, SALT8, V21_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(V21, NORD1, PNOR, PNOR_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(V21, GPIOAA1, GPIOAA1);
+ PIN_DECL_(V21, SIG_EXPR_LIST_PTR(V21, VPOR3), SIG_EXPR_LIST_PTR(V21, SALT8),
+               SIG_EXPR_LIST_PTR(V21, NORD1), SIG_EXPR_LIST_PTR(V21, GPIOAA1));
  FUNC_GROUP_DECL(SALT8, V21);
  
  #define Y22 210
  #define Y22_DESC      SIG_DESC_SET(SCUA4, 26)
- SIG_EXPR_DECL(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_LIST_DECL(VPOR4, SIG_EXPR_PTR(VPOR4, VPO),
-               SIG_EXPR_PTR(VPOR4, VPOOFF1), SIG_EXPR_PTR(VPOR4, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(SALT9, SALT9, Y22_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(NORD2, PNOR, PNOR_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(GPIOAA2, GPIOAA2);
- MS_PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(VPOR4), SIG_EXPR_LIST_PTR(SALT9),
-               SIG_EXPR_LIST_PTR(NORD2), SIG_EXPR_LIST_PTR(GPIOAA2));
+ SIG_EXPR_DECL_SINGLE(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_LIST_DECL(VPOR4, VPO,
+               SIG_EXPR_PTR(VPOR4, VPO),
+               SIG_EXPR_PTR(VPOR4, VPOOFF1),
+               SIG_EXPR_PTR(VPOR4, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(Y22, VPOR4, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(Y22, SALT9, SALT9, Y22_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(Y22, NORD2, PNOR, PNOR_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(Y22, GPIOAA2, GPIOAA2);
+ PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(Y22, VPOR4), SIG_EXPR_LIST_PTR(Y22, SALT9),
+               SIG_EXPR_LIST_PTR(Y22, NORD2), SIG_EXPR_LIST_PTR(Y22, GPIOAA2));
  FUNC_GROUP_DECL(SALT9, Y22);
  
  #define AA22 211
  #define AA22_DESC     SIG_DESC_SET(SCUA4, 27)
- SIG_EXPR_DECL(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_LIST_DECL(VPOR5, SIG_EXPR_PTR(VPOR5, VPO),
-               SIG_EXPR_PTR(VPOR5, VPOOFF1), SIG_EXPR_PTR(VPOR5, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(SALT10, SALT10, AA22_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(NORD3, PNOR, PNOR_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(GPIOAA3, GPIOAA3);
- MS_PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(VPOR5), SIG_EXPR_LIST_PTR(SALT10),
-               SIG_EXPR_LIST_PTR(NORD3), SIG_EXPR_LIST_PTR(GPIOAA3));
+ SIG_EXPR_DECL_SINGLE(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_LIST_DECL(VPOR5, VPO,
+               SIG_EXPR_PTR(VPOR5, VPO),
+               SIG_EXPR_PTR(VPOR5, VPOOFF1),
+               SIG_EXPR_PTR(VPOR5, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(AA22, VPOR5, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(AA22, SALT10, SALT10, AA22_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(AA22, NORD3, PNOR, PNOR_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(AA22, GPIOAA3, GPIOAA3);
+ PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(AA22, VPOR5),
+         SIG_EXPR_LIST_PTR(AA22, SALT10), SIG_EXPR_LIST_PTR(AA22, NORD3),
+         SIG_EXPR_LIST_PTR(AA22, GPIOAA3));
  FUNC_GROUP_DECL(SALT10, AA22);
  
  #define U22 212
  #define U22_DESC      SIG_DESC_SET(SCUA4, 28)
- SIG_EXPR_DECL(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_LIST_DECL(VPOR6, SIG_EXPR_PTR(VPOR6, VPO),
-               SIG_EXPR_PTR(VPOR6, VPOOFF1), SIG_EXPR_PTR(VPOR6, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(SALT11, SALT11, U22_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(NORD4, PNOR, PNOR_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(GPIOAA4, GPIOAA4);
- MS_PIN_DECL_(U22, SIG_EXPR_LIST_PTR(VPOR6), SIG_EXPR_LIST_PTR(SALT11),
-               SIG_EXPR_LIST_PTR(NORD4), SIG_EXPR_LIST_PTR(GPIOAA4));
+ SIG_EXPR_DECL_SINGLE(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_LIST_DECL(VPOR6, VPO,
+               SIG_EXPR_PTR(VPOR6, VPO),
+               SIG_EXPR_PTR(VPOR6, VPOOFF1),
+               SIG_EXPR_PTR(VPOR6, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(U22, VPOR6, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(U22, SALT11, SALT11, U22_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(U22, NORD4, PNOR, PNOR_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(U22, GPIOAA4, GPIOAA4);
+ PIN_DECL_(U22, SIG_EXPR_LIST_PTR(U22, VPOR6), SIG_EXPR_LIST_PTR(U22, SALT11),
+               SIG_EXPR_LIST_PTR(U22, NORD4), SIG_EXPR_LIST_PTR(U22, GPIOAA4));
  FUNC_GROUP_DECL(SALT11, U22);
  
  #define T20 213
  #define T20_DESC      SIG_DESC_SET(SCUA4, 29)
- SIG_EXPR_DECL(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_LIST_DECL(VPOR7, SIG_EXPR_PTR(VPOR7, VPO),
-               SIG_EXPR_PTR(VPOR7, VPOOFF1), SIG_EXPR_PTR(VPOR7, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(SALT12, SALT12, T20_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(NORD5, PNOR, PNOR_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(GPIOAA5, GPIOAA5);
- MS_PIN_DECL_(T20, SIG_EXPR_LIST_PTR(VPOR7), SIG_EXPR_LIST_PTR(SALT12),
-               SIG_EXPR_LIST_PTR(NORD5), SIG_EXPR_LIST_PTR(GPIOAA5));
+ SIG_EXPR_DECL_SINGLE(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_LIST_DECL(VPOR7, VPO,
+               SIG_EXPR_PTR(VPOR7, VPO),
+               SIG_EXPR_PTR(VPOR7, VPOOFF1),
+               SIG_EXPR_PTR(VPOR7, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(T20, VPOR7, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(T20, SALT12, SALT12, T20_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(T20, NORD5, PNOR, PNOR_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(T20, GPIOAA5, GPIOAA5);
+ PIN_DECL_(T20, SIG_EXPR_LIST_PTR(T20, VPOR7), SIG_EXPR_LIST_PTR(T20, SALT12),
+               SIG_EXPR_LIST_PTR(T20, NORD5), SIG_EXPR_LIST_PTR(T20, GPIOAA5));
  FUNC_GROUP_DECL(SALT12, T20);
  
  #define N18 214
  #define N18_DESC      SIG_DESC_SET(SCUA4, 30)
- SIG_EXPR_DECL(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_LIST_DECL(VPOR8, SIG_EXPR_PTR(VPOR8, VPO),
-               SIG_EXPR_PTR(VPOR8, VPOOFF1), SIG_EXPR_PTR(VPOR8, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(SALT13, SALT13, N18_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(NORD6, PNOR, PNOR_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(GPIOAA6, GPIOAA6);
- MS_PIN_DECL_(N18, SIG_EXPR_LIST_PTR(VPOR8), SIG_EXPR_LIST_PTR(SALT13),
-               SIG_EXPR_LIST_PTR(NORD6), SIG_EXPR_LIST_PTR(GPIOAA6));
+ SIG_EXPR_DECL_SINGLE(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_LIST_DECL(VPOR8, VPO,
+               SIG_EXPR_PTR(VPOR8, VPO),
+               SIG_EXPR_PTR(VPOR8, VPOOFF1),
+               SIG_EXPR_PTR(VPOR8, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(N18, VPOR8, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(N18, SALT13, SALT13, N18_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(N18, NORD6, PNOR, PNOR_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(N18, GPIOAA6, GPIOAA6);
+ PIN_DECL_(N18, SIG_EXPR_LIST_PTR(N18, VPOR8), SIG_EXPR_LIST_PTR(N18, SALT13),
+               SIG_EXPR_LIST_PTR(N18, NORD6), SIG_EXPR_LIST_PTR(N18, GPIOAA6));
  FUNC_GROUP_DECL(SALT13, N18);
  
  #define P19 215
  #define P19_DESC      SIG_DESC_SET(SCUA4, 31)
- SIG_EXPR_DECL(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_DECL(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
- SIG_EXPR_LIST_DECL(VPOR9, SIG_EXPR_PTR(VPOR9, VPO),
-               SIG_EXPR_PTR(VPOR9, VPOOFF1), SIG_EXPR_PTR(VPOR9, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(SALT14, SALT14, P19_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(NORD7, PNOR, PNOR_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(GPIOAA7, GPIOAA7);
- MS_PIN_DECL_(P19, SIG_EXPR_LIST_PTR(VPOR9), SIG_EXPR_LIST_PTR(SALT14),
-               SIG_EXPR_LIST_PTR(NORD7), SIG_EXPR_LIST_PTR(GPIOAA7));
+ SIG_EXPR_DECL_SINGLE(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+ SIG_EXPR_LIST_DECL(VPOR9, VPO,
+               SIG_EXPR_PTR(VPOR9, VPO),
+               SIG_EXPR_PTR(VPOR9, VPOOFF1),
+               SIG_EXPR_PTR(VPOR9, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(P19, VPOR9, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(P19, SALT14, SALT14, P19_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(P19, NORD7, PNOR, PNOR_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(P19, GPIOAA7, GPIOAA7);
+ PIN_DECL_(P19, SIG_EXPR_LIST_PTR(P19, VPOR9), SIG_EXPR_LIST_PTR(P19, SALT14),
+               SIG_EXPR_LIST_PTR(P19, NORD7), SIG_EXPR_LIST_PTR(P19, GPIOAA7));
  FUNC_GROUP_DECL(SALT14, P19);
  
  #define N19 216
  #define N19_DESC      SIG_DESC_SET(SCUA8, 0)
- SIG_EXPR_DECL(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPODE, SIG_EXPR_PTR(VPODE, VPO),
-               SIG_EXPR_PTR(VPODE, VPOOFF1), SIG_EXPR_PTR(VPODE, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(NOROE, PNOR, PNOR_DESC);
- MS_PIN_DECL(N19, GPIOAB0, VPODE, NOROE);
+ SIG_EXPR_DECL_SINGLE(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPODE, VPO,
+               SIG_EXPR_PTR(VPODE, VPO),
+               SIG_EXPR_PTR(VPODE, VPOOFF1),
+               SIG_EXPR_PTR(VPODE, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(N19, VPODE, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(N19, NOROE, PNOR, PNOR_DESC);
+ PIN_DECL_2(N19, GPIOAB0, VPODE, NOROE);
  
  #define T21 217
  #define T21_DESC      SIG_DESC_SET(SCUA8, 1)
- SIG_EXPR_DECL(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOHS, SIG_EXPR_PTR(VPOHS, VPO),
-               SIG_EXPR_PTR(VPOHS, VPOOFF1), SIG_EXPR_PTR(VPOHS, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(NORWE, PNOR, PNOR_DESC);
- MS_PIN_DECL(T21, GPIOAB1, VPOHS, NORWE);
+ SIG_EXPR_DECL_SINGLE(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOHS, VPO,
+               SIG_EXPR_PTR(VPOHS, VPO),
+               SIG_EXPR_PTR(VPOHS, VPOOFF1),
+               SIG_EXPR_PTR(VPOHS, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(T21, VPOHS, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(T21, NORWE, PNOR, PNOR_DESC);
+ PIN_DECL_2(T21, GPIOAB1, VPOHS, NORWE);
  
  FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22,
                AA22, U22, T20, N18, P19, N19, T21);
  
  #define T22 218
  #define T22_DESC      SIG_DESC_SET(SCUA8, 2)
- SIG_EXPR_DECL(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOVS, SIG_EXPR_PTR(VPOVS, VPO),
-               SIG_EXPR_PTR(VPOVS, VPOOFF1), SIG_EXPR_PTR(VPOVS, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, T22_DESC);
- MS_PIN_DECL(T22, GPIOAB2, VPOVS, WDTRST1);
+ SIG_EXPR_DECL_SINGLE(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOVS, VPO,
+               SIG_EXPR_PTR(VPOVS, VPO),
+               SIG_EXPR_PTR(VPOVS, VPOOFF1),
+               SIG_EXPR_PTR(VPOVS, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(T22, VPOVS, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(T22, WDTRST1, WDTRST1, T22_DESC);
+ PIN_DECL_2(T22, GPIOAB2, VPOVS, WDTRST1);
  FUNC_GROUP_DECL(WDTRST1, T22);
  
  #define R20 219
  #define R20_DESC      SIG_DESC_SET(SCUA8, 3)
- SIG_EXPR_DECL(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_DECL(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
- SIG_EXPR_LIST_DECL(VPOCLK, SIG_EXPR_PTR(VPOCLK, VPO),
-               SIG_EXPR_PTR(VPOCLK, VPOOFF1), SIG_EXPR_PTR(VPOCLK, VPOOFF2));
- SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, R20_DESC);
- MS_PIN_DECL(R20, GPIOAB3, VPOCLK, WDTRST2);
+ SIG_EXPR_DECL_SINGLE(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+ SIG_EXPR_LIST_DECL(VPOCLK, VPO,
+               SIG_EXPR_PTR(VPOCLK, VPO),
+               SIG_EXPR_PTR(VPOCLK, VPOOFF1),
+               SIG_EXPR_PTR(VPOCLK, VPOOFF2));
+ SIG_EXPR_LIST_ALIAS(R20, VPOCLK, VPO);
+ SIG_EXPR_LIST_DECL_SINGLE(R20, WDTRST2, WDTRST2, R20_DESC);
+ PIN_DECL_2(R20, GPIOAB3, VPOCLK, WDTRST2);
  FUNC_GROUP_DECL(WDTRST2, R20);
  
  FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20,
@@@ -1699,64 -1802,64 +1802,64 @@@
  #define ESPI_DESC     SIG_DESC_SET(HW_STRAP1, 25)
  
  #define G21 224
- SIG_EXPR_LIST_DECL_SINGLE(ESPID0, ESPI, ESPI_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(LAD0, LAD0, SIG_DESC_SET(SCUAC, 0));
- MS_PIN_DECL(G21, GPIOAC0, ESPID0, LAD0);
+ SIG_EXPR_LIST_DECL_SINGLE(G21, ESPID0, ESPI, ESPI_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(G21, LAD0, LAD0, SIG_DESC_SET(SCUAC, 0));
+ PIN_DECL_2(G21, GPIOAC0, ESPID0, LAD0);
  FUNC_GROUP_DECL(LAD0, G21);
  
  #define G20 225
- SIG_EXPR_LIST_DECL_SINGLE(ESPID1, ESPI, ESPI_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(LAD1, LAD1, SIG_DESC_SET(SCUAC, 1));
- MS_PIN_DECL(G20, GPIOAC1, ESPID1, LAD1);
+ SIG_EXPR_LIST_DECL_SINGLE(G20, ESPID1, ESPI, ESPI_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(G20, LAD1, LAD1, SIG_DESC_SET(SCUAC, 1));
+ PIN_DECL_2(G20, GPIOAC1, ESPID1, LAD1);
  FUNC_GROUP_DECL(LAD1, G20);
  
  #define D22 226
- SIG_EXPR_LIST_DECL_SINGLE(ESPID2, ESPI, ESPI_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(LAD2, LAD2, SIG_DESC_SET(SCUAC, 2));
- MS_PIN_DECL(D22, GPIOAC2, ESPID2, LAD2);
+ SIG_EXPR_LIST_DECL_SINGLE(D22, ESPID2, ESPI, ESPI_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(D22, LAD2, LAD2, SIG_DESC_SET(SCUAC, 2));
+ PIN_DECL_2(D22, GPIOAC2, ESPID2, LAD2);
  FUNC_GROUP_DECL(LAD2, D22);
  
  #define E22 227
- SIG_EXPR_LIST_DECL_SINGLE(ESPID3, ESPI, ESPI_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(LAD3, LAD3, SIG_DESC_SET(SCUAC, 3));
- MS_PIN_DECL(E22, GPIOAC3, ESPID3, LAD3);
+ SIG_EXPR_LIST_DECL_SINGLE(E22, ESPID3, ESPI, ESPI_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(E22, LAD3, LAD3, SIG_DESC_SET(SCUAC, 3));
+ PIN_DECL_2(E22, GPIOAC3, ESPID3, LAD3);
  FUNC_GROUP_DECL(LAD3, E22);
  
  #define C22 228
- SIG_EXPR_LIST_DECL_SINGLE(ESPICK, ESPI, ESPI_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(LCLK, LCLK, SIG_DESC_SET(SCUAC, 4));
- MS_PIN_DECL(C22, GPIOAC4, ESPICK, LCLK);
+ SIG_EXPR_LIST_DECL_SINGLE(C22, ESPICK, ESPI, ESPI_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(C22, LCLK, LCLK, SIG_DESC_SET(SCUAC, 4));
+ PIN_DECL_2(C22, GPIOAC4, ESPICK, LCLK);
  FUNC_GROUP_DECL(LCLK, C22);
  
  #define F21 229
- SIG_EXPR_LIST_DECL_SINGLE(ESPICS, ESPI, ESPI_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5));
- MS_PIN_DECL(F21, GPIOAC5, ESPICS, LFRAME);
+ SIG_EXPR_LIST_DECL_SINGLE(F21, ESPICS, ESPI, ESPI_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(F21, LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5));
+ PIN_DECL_2(F21, GPIOAC5, ESPICS, LFRAME);
  FUNC_GROUP_DECL(LFRAME, F21);
  
  #define F22 230
- SIG_EXPR_LIST_DECL_SINGLE(ESPIALT, ESPI, ESPI_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6));
- MS_PIN_DECL(F22, GPIOAC6, ESPIALT, LSIRQ);
+ SIG_EXPR_LIST_DECL_SINGLE(F22, ESPIALT, ESPI, ESPI_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(F22, LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6));
+ PIN_DECL_2(F22, GPIOAC6, ESPIALT, LSIRQ);
  FUNC_GROUP_DECL(LSIRQ, F22);
  
  #define G22 231
- SIG_EXPR_LIST_DECL_SINGLE(ESPIRST, ESPI, ESPI_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7));
- MS_PIN_DECL(G22, GPIOAC7, ESPIRST, LPCRST);
+ SIG_EXPR_LIST_DECL_SINGLE(G22, ESPIRST, ESPI, ESPI_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(G22, LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7));
+ PIN_DECL_2(G22, GPIOAC7, ESPIRST, LPCRST);
  FUNC_GROUP_DECL(LPCRST, G22);
  
  FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22);
  
  #define A7 232
- SIG_EXPR_LIST_DECL_SINGLE(USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29));
- SIG_EXPR_LIST_DECL_SINGLE(USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
- MS_PIN_DECL_(A7, SIG_EXPR_LIST_PTR(USB2AHDP), SIG_EXPR_LIST_PTR(USB2ADDP));
+ SIG_EXPR_LIST_DECL_SINGLE(A7, USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29));
+ SIG_EXPR_LIST_DECL_SINGLE(A7, USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
+ PIN_DECL_(A7, SIG_EXPR_LIST_PTR(A7, USB2AHDP), SIG_EXPR_LIST_PTR(A7, USB2ADDP));
  
  #define A8 233
- SIG_EXPR_LIST_DECL_SINGLE(USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29));
- SIG_EXPR_LIST_DECL_SINGLE(USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
- MS_PIN_DECL_(A8, SIG_EXPR_LIST_PTR(USB2AHDN), SIG_EXPR_LIST_PTR(USB2ADDN));
+ SIG_EXPR_LIST_DECL_SINGLE(A8, USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29));
+ SIG_EXPR_LIST_DECL_SINGLE(A8, USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
+ PIN_DECL_(A8, SIG_EXPR_LIST_PTR(A8, USB2AHDN), SIG_EXPR_LIST_PTR(A8, USB2ADDN));
  
  FUNC_GROUP_DECL(USB2AH, A7, A8);
  FUNC_GROUP_DECL(USB2AD, A7, A8);
@@@ -1767,24 -1870,28 +1870,28 @@@
  #define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }
  
  #define B6 234
- SIG_EXPR_LIST_DECL_SINGLE(USB11BDP, USB11BHID, USB11BHID_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(USB2BDDP, USB2BD, USB2BD_DESC);
- SIG_EXPR_DECL(USB2BHDP1, USB2BH, USB2BH1_DESC);
- SIG_EXPR_DECL(USB2BHDP2, USB2BH, USB2BH2_DESC);
- SIG_EXPR_LIST_DECL(USB2BHDP, SIG_EXPR_PTR(USB2BHDP1, USB2BH),
+ SIG_EXPR_LIST_DECL_SINGLE(B6, USB11BDP, USB11BHID, USB11BHID_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(B6, USB2BDDP, USB2BD, USB2BD_DESC);
+ SIG_EXPR_DECL_SINGLE(USB2BHDP1, USB2BH, USB2BH1_DESC);
+ SIG_EXPR_DECL_SINGLE(USB2BHDP2, USB2BH, USB2BH2_DESC);
+ SIG_EXPR_LIST_DECL(USB2BHDP, USB2BH,
+               SIG_EXPR_PTR(USB2BHDP1, USB2BH),
                SIG_EXPR_PTR(USB2BHDP2, USB2BH));
- MS_PIN_DECL_(B6, SIG_EXPR_LIST_PTR(USB11BDP), SIG_EXPR_LIST_PTR(USB2BDDP),
-               SIG_EXPR_LIST_PTR(USB2BHDP));
+ SIG_EXPR_LIST_ALIAS(B6, USB2BHDP, USB2BH);
+ PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDP), SIG_EXPR_LIST_PTR(B6, USB2BDDP),
+               SIG_EXPR_LIST_PTR(B6, USB2BHDP));
  
  #define A6 235
- SIG_EXPR_LIST_DECL_SINGLE(USB11BDN, USB11BHID, USB11BHID_DESC);
- SIG_EXPR_LIST_DECL_SINGLE(USB2BDN, USB2BD, USB2BD_DESC);
- SIG_EXPR_DECL(USB2BHDN1, USB2BH, USB2BH1_DESC);
- SIG_EXPR_DECL(USB2BHDN2, USB2BH, USB2BH2_DESC);
- SIG_EXPR_LIST_DECL(USB2BHDN, SIG_EXPR_PTR(USB2BHDN1, USB2BH),
+ SIG_EXPR_LIST_DECL_SINGLE(A6, USB11BDN, USB11BHID, USB11BHID_DESC);
+ SIG_EXPR_LIST_DECL_SINGLE(A6, USB2BDN, USB2BD, USB2BD_DESC);
+ SIG_EXPR_DECL_SINGLE(USB2BHDN1, USB2BH, USB2BH1_DESC);
+ SIG_EXPR_DECL_SINGLE(USB2BHDN2, USB2BH, USB2BH2_DESC);
+ SIG_EXPR_LIST_DECL(USB2BHDN, USB2BH,
+               SIG_EXPR_PTR(USB2BHDN1, USB2BH),
                SIG_EXPR_PTR(USB2BHDN2, USB2BH));
- MS_PIN_DECL_(A6, SIG_EXPR_LIST_PTR(USB11BDN), SIG_EXPR_LIST_PTR(USB2BDN),
-               SIG_EXPR_LIST_PTR(USB2BHDN));
+ SIG_EXPR_LIST_ALIAS(A6, USB2BHDN, USB2BH);
+ PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDN), SIG_EXPR_LIST_PTR(A6, USB2BDN),
+               SIG_EXPR_LIST_PTR(A6, USB2BHDN));
  
  FUNC_GROUP_DECL(USB11BHID, B6, A6);
  FUNC_GROUP_DECL(USB2BD, B6, A6);
@@@ -2552,7 -2659,7 +2659,7 @@@ static struct regmap *aspeed_g5_acquire
                        if (IS_ERR(map))
                                return map;
                } else
 -                      map = ERR_PTR(-ENODEV);
 +                      return ERR_PTR(-ENODEV);
  
                ctx->maps[ASPEED_IP_LPC] = map;
                dev_dbg(ctx->dev, "Acquired LPC regmap");
@@@ -2562,33 -2669,6 +2669,33 @@@
        return ERR_PTR(-EINVAL);
  }
  
 +static int aspeed_g5_sig_expr_eval(struct aspeed_pinmux_data *ctx,
 +                                 const struct aspeed_sig_expr *expr,
 +                                 bool enabled)
 +{
 +      int ret;
 +      int i;
 +
 +      for (i = 0; i < expr->ndescs; i++) {
 +              const struct aspeed_sig_desc *desc = &expr->descs[i];
 +              struct regmap *map;
 +
 +              map = aspeed_g5_acquire_regmap(ctx, desc->ip);
 +              if (IS_ERR(map)) {
 +                      dev_err(ctx->dev,
 +                              "Failed to acquire regmap for IP block %d\n",
 +                              desc->ip);
 +                      return PTR_ERR(map);
 +              }
 +
 +              ret = aspeed_sig_desc_eval(desc, enabled, ctx->maps[desc->ip]);
 +              if (ret <= 0)
 +                      return ret;
 +      }
 +
 +      return 1;
 +}
 +
  /**
   * Configure a pin's signal by applying an expression's descriptor state for
   * all descriptors in the expression.
@@@ -2674,7 -2754,6 +2781,7 @@@ static int aspeed_g5_sig_expr_set(struc
  }
  
  static const struct aspeed_pinmux_ops aspeed_g5_ops = {
 +      .eval = aspeed_g5_sig_expr_eval,
        .set = aspeed_g5_sig_expr_set,
  };
  
@@@ -2742,6 -2821,10 +2849,10 @@@ static int aspeed_g5_pinctrl_probe(stru
  
  static const struct of_device_id aspeed_g5_pinctrl_of_match[] = {
        { .compatible = "aspeed,ast2500-pinctrl", },
+       /*
+        * The aspeed,g5-pinctrl compatible has been removed the from the
+        * bindings, but keep the match in case of old devicetrees.
+        */
        { .compatible = "aspeed,g5-pinctrl", },
        { },
  };

diff --combined drivers/pinctrl/aspeed/pinmux-aspeed.h
index db3457c86f48c5f0314ce917b6c6136560975e86,dfcc97ca1a8bd1498a87c4c488e540b5e9f53dbe..a2c0d52e4f7b654cb360e91aa7227a8abaa295ac
--- 1/drivers/pinctrl/aspeed/pinmux-aspeed.h
--- 2/drivers/pinctrl/aspeed/pinmux-aspeed.h
+++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h
@@@ -162,10 -162,11 +162,11 @@@
   * * Enabling lower priority signals requires higher priority signals be
   *   disabled
   *
-  * * A function represents a set of signals; functions are distinct if their
-  *   sets of signals are not equal
+  * * A function represents a set of signals; functions are distinct if they
+  *   do not share a subset of signals (and may be distinct if they are a
+  *   strict subset).
   *
-  * * Signals participate in one or more functions
+  * * Signals participate in one or more functions or groups
   *
   * * A function is described by an expression of one or more signal
   *   descriptors, which compare bit values in a register
@@@ -507,20 -508,21 +508,21 @@@ struct aspeed_pin_desc 
   * @idx: The bit index in the register
   */
  #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
+ #define SIG_DESC_CLEAR(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 0)
  
- #define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func
- #define SIG_DESC_LIST_DECL(sig, func, ...) \
-       static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \
+ #define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group
+ #define SIG_DESC_LIST_DECL(sig, group, ...) \
+       static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, group)[] = \
                { __VA_ARGS__ }
  
- #define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func
- #define SIG_EXPR_DECL_(sig, func) \
-       static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \
+ #define SIG_EXPR_SYM(sig, group) sig_expr_ ## sig ## _ ## group
+ #define SIG_EXPR_DECL_(sig, group, func) \
+       static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, group) = \
        { \
                .signal = #sig, \
                .function = #func, \
-               .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \
-               .descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \
+               .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, group)), \
+               .descs = &(SIG_DESC_LIST_SYM(sig, group))[0], \
        }
  
  /**
@@@ -533,16 -535,16 +535,16 @@@
   *
   * For example, the following declares the ROMD8 signal for the ROM16 function:
   *
-  *     SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
+  *     SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6));
   *
   * And with multiple signal descriptors:
   *
-  *     SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
+  *     SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
   *              { HW_STRAP1, GENMASK(1, 0), 0, 0 });
   */
- #define SIG_EXPR_DECL(sig, func, ...) \
-       SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
-       SIG_EXPR_DECL_(sig, func)
+ #define SIG_EXPR_DECL(sig, group, func, ...) \
+       SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \
+       SIG_EXPR_DECL_(sig, group, func)
  
  /**
   * Declare a pointer to a signal expression
@@@ -550,9 -552,9 +552,9 @@@
   * @sig: The macro symbol name for the signal (subjected to token pasting)
   * @func: The macro symbol name for the function (subjected to token pasting)
   */
- #define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func))
+ #define SIG_EXPR_PTR(sig, group) (&SIG_EXPR_SYM(sig, group))
  
- #define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig
+ #define SIG_EXPR_LIST_SYM(sig, group) sig_exprs_ ## sig ## _ ## group
  
  /**
   * Declare a signal expression list for reference in a struct aspeed_pin_prio.
@@@ -563,79 -565,100 +565,100 @@@
   * For example, the 16-bit ROM bus can be enabled by one of two possible signal
   * expressions:
   *
-  *     SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
-  *     SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
+  *     SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6));
+  *     SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
   *              { HW_STRAP1, GENMASK(1, 0), 0, 0 });
   *     SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
   *              SIG_EXPR_PTR(ROMD8, ROM16S));
   */
- #define SIG_EXPR_LIST_DECL(sig, ...) \
-       static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \
+ #define SIG_EXPR_LIST_DECL(sig, group, ...) \
+       static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig, group)[] =\
                { __VA_ARGS__, NULL }
  
+ #define stringify(x) #x
+ #define istringify(x) stringify(x)
+ 
+ /**
+  * Create an expression symbol alias from (signal, group) to (pin, signal).
+  *
+  * @pin: The pin number
+  * @sig: The signal name
+  * @group: The name of the group of which the pin is a member that is
+  *         associated with the function's signal
+  *
+  * Using an alias in this way enables detection of copy/paste errors (defining
+  * the signal for a group multiple times) whilst enabling multiple pin groups
+  * to exist for a signal without intrusive side-effects on defining the list of
+  * signals available on a pin.
+  */
+ #define SIG_EXPR_LIST_ALIAS(pin, sig, group) \
+       static const struct aspeed_sig_expr *\
+               SIG_EXPR_LIST_SYM(pin, sig)[ARRAY_SIZE(SIG_EXPR_LIST_SYM(sig, group))] \
+               __attribute__((alias(istringify(SIG_EXPR_LIST_SYM(sig, group)))))
+ 
  /**
   * A short-hand macro for declaring a function expression and an expression
-  * list with a single function.
+  * list with a single expression (SE) and a single group (SG) of pins.
   *
-  * @func: A macro symbol name for the function (is subjected to token pasting)
+  * @pin: The pin the signal will be routed to
+  * @sig: The signal that will be routed to the pin for the function
+  * @func: A macro symbol name for the function
   * @...: Function descriptors that define the function expression
   *
   * For example, signal NCTS6 participates in its own function with one group:
   *
-  *     SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
+  *     SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
   */
- #define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \
+ #define SIG_EXPR_LIST_DECL_SESG(pin, sig, func, ...) \
        SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
-       SIG_EXPR_DECL_(sig, func); \
-       SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func))
+       SIG_EXPR_DECL_(sig, func, func); \
+       SIG_EXPR_LIST_DECL(sig, func, SIG_EXPR_PTR(sig, func)); \
+       SIG_EXPR_LIST_ALIAS(pin, sig, func)
+ 
+ /**
+  * Similar to the above, but for pins with a single expression (SE) and
+  * multiple groups (MG) of pins.
+  *
+  * @pin: The pin the signal will be routed to
+  * @sig: The signal that will be routed to the pin for the function
+  * @group: The name of the function's pin group in which the pin participates
+  * @func: A macro symbol name for the function
+  * @...: Function descriptors that define the function expression
+  */
+ #define SIG_EXPR_LIST_DECL_SEMG(pin, sig, group, func, ...) \
+       SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \
+       SIG_EXPR_DECL_(sig, group, func); \
+       SIG_EXPR_LIST_DECL(sig, group, SIG_EXPR_PTR(sig, group)); \
+       SIG_EXPR_LIST_ALIAS(pin, sig, group)
  
- #define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \
-       SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1))
+ /**
+  * Similar to the above, but for pins with a dual expressions (DE) and
+  * and a single group (SG) of pins.
+  *
+  * @pin: The pin the signal will be routed to
+  * @sig: The signal that will be routed to the pin for the function
+  * @group: The name of the function's pin group in which the pin participates
+  * @func: A macro symbol name for the function
+  * @...: Function descriptors that define the function expression
+  */
+ #define SIG_EXPR_LIST_DECL_DESG(pin, sig, f0, f1) \
+       SIG_EXPR_LIST_DECL(sig, f0, \
+                          SIG_EXPR_PTR(sig, f0), \
+                          SIG_EXPR_PTR(sig, f1)); \
+       SIG_EXPR_LIST_ALIAS(pin, sig, f0)
  
- #define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0])
+ #define SIG_EXPR_LIST_PTR(sig, group) SIG_EXPR_LIST_SYM(sig, group)
  
  #define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin
  #define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0])
  #define PIN_SYM(pin) pin_ ## pin
  
- #define MS_PIN_DECL_(pin, ...) \
+ #define PIN_DECL_(pin, ...) \
        static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
                { __VA_ARGS__, NULL }; \
        static const struct aspeed_pin_desc PIN_SYM(pin) = \
                { #pin, PIN_EXPRS_PTR(pin) }
  
- /**
-  * Declare a multi-signal pin
-  *
-  * @pin: The pin number
-  * @other: Macro name for "other" functionality (subjected to stringification)
-  * @high: Macro name for the highest priority signal functions
-  * @low: Macro name for the low signal functions
-  *
-  * For example:
-  *
-  *     #define A8 56
-  *     SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
-  *     SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
-  *              { HW_STRAP1, GENMASK(1, 0), 0, 0 });
-  *     SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
-  *              SIG_EXPR_PTR(ROMD8, ROM16S));
-  *     SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
-  *     MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6);
-  */
- #define MS_PIN_DECL(pin, other, high, low) \
-       SIG_EXPR_LIST_DECL_SINGLE(other, other); \
-       MS_PIN_DECL_(pin, \
-                       SIG_EXPR_LIST_PTR(high), \
-                       SIG_EXPR_LIST_PTR(low), \
-                       SIG_EXPR_LIST_PTR(other))
- 
- #define PIN_GROUP_SYM(func) pins_ ## func
- #define FUNC_GROUP_SYM(func) groups_ ## func
- #define FUNC_GROUP_DECL(func, ...) \
-       static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \
-       static const char *FUNC_GROUP_SYM(func)[] = { #func }
- 
  /**
   * Declare a single signal pin
   *
@@@ -647,11 -670,12 +670,12 @@@
   *
   *     #define E3 80
   *     SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
-  *     SS_PIN_DECL(E3, GPIOK0, SCL5);
+  *     PIN_DECL_1(E3, GPIOK0, SCL5);
   */
- #define SS_PIN_DECL(pin, other, sig) \
-       SIG_EXPR_LIST_DECL_SINGLE(other, other); \
-       MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other))
+ #define PIN_DECL_1(pin, other, sig) \
+       SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
+       PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
+                 SIG_EXPR_LIST_PTR(pin, other))
  
  /**
   * Single signal, single function pin declaration
@@@ -666,14 -690,63 +690,63 @@@
   *    SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
   */
  #define SSSF_PIN_DECL(pin, other, sig, ...) \
-       SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \
-       SIG_EXPR_LIST_DECL_SINGLE(other, other); \
-       MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \
+       SIG_EXPR_LIST_DECL_SESG(pin, sig, sig, __VA_ARGS__); \
+       SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
+       PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
+                 SIG_EXPR_LIST_PTR(pin, other)); \
        FUNC_GROUP_DECL(sig, pin)
+ /**
+  * Declare a two-signal pin
+  *
+  * @pin: The pin number
+  * @other: Macro name for "other" functionality (subjected to stringification)
+  * @high: Macro name for the highest priority signal functions
+  * @low: Macro name for the low signal functions
+  *
+  * For example:
+  *
+  *     #define A8 56
+  *     SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
+  *     SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
+  *              { HW_STRAP1, GENMASK(1, 0), 0, 0 });
+  *     SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
+  *              SIG_EXPR_PTR(ROMD8, ROM16S));
+  *     SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
+  *     PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6);
+  */
+ #define PIN_DECL_2(pin, other, high, low) \
+       SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
+       PIN_DECL_(pin, \
+                       SIG_EXPR_LIST_PTR(pin, high), \
+                       SIG_EXPR_LIST_PTR(pin, low), \
+                       SIG_EXPR_LIST_PTR(pin, other))
+ 
+ #define PIN_DECL_3(pin, other, high, medium, low) \
+       SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
+       PIN_DECL_(pin, \
+                       SIG_EXPR_LIST_PTR(pin, high), \
+                       SIG_EXPR_LIST_PTR(pin, medium), \
+                       SIG_EXPR_LIST_PTR(pin, low), \
+                       SIG_EXPR_LIST_PTR(pin, other))
+ 
+ #define GROUP_SYM(group) group_pins_ ## group
+ #define GROUP_DECL(group, ...) \
+       static const int GROUP_SYM(group)[] = { __VA_ARGS__ }
+ 
+ #define FUNC_SYM(func) func_groups_ ## func
+ #define FUNC_DECL_(func, ...) \
+       static const char *FUNC_SYM(func)[] = { __VA_ARGS__ }
+ 
+ #define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two)
+ 
+ #define FUNC_GROUP_DECL(func, ...) \
+       GROUP_DECL(func, __VA_ARGS__); \
+       FUNC_DECL_(func, #func)
+ 
  
  #define GPIO_PIN_DECL(pin, gpio) \
-       SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \
-       MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio))
+       SIG_EXPR_LIST_DECL_SESG(pin, gpio, gpio); \
+       PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, gpio))
  
  struct aspeed_pin_group {
        const char *name;
@@@ -683,8 -756,8 +756,8 @@@
  
  #define ASPEED_PINCTRL_GROUP(name_) { \
        .name = #name_, \
-       .pins = &(PIN_GROUP_SYM(name_))[0], \
-       .npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \
+       .pins = &(GROUP_SYM(name_))[0], \
+       .npins = ARRAY_SIZE(GROUP_SYM(name_)), \
  }
  
  struct aspeed_pin_function {
@@@ -695,15 -768,13 +768,15 @@@
  
  #define ASPEED_PINCTRL_FUNC(name_, ...) { \
        .name = #name_, \
-       .groups = &FUNC_GROUP_SYM(name_)[0], \
-       .ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \
+       .groups = &FUNC_SYM(name_)[0], \
+       .ngroups = ARRAY_SIZE(FUNC_SYM(name_)), \
  }
  
  struct aspeed_pinmux_data;
  
  struct aspeed_pinmux_ops {
 +      int (*eval)(struct aspeed_pinmux_data *ctx,
 +                  const struct aspeed_sig_expr *expr, bool enabled);
        int (*set)(struct aspeed_pinmux_data *ctx,
                   const struct aspeed_sig_expr *expr, bool enabled);
  };
@@@ -724,8 -795,9 +797,8 @@@ struct aspeed_pinmux_data 
  int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, bool enabled,
                         struct regmap *map);
  
 -int aspeed_sig_expr_eval(const struct aspeed_pinmux_data *ctx,
 -                       const struct aspeed_sig_expr *expr,
 -                       bool enabled);
 +int aspeed_sig_expr_eval(struct aspeed_pinmux_data *ctx,
 +                       const struct aspeed_sig_expr *expr, bool enabled);
  
  static inline int aspeed_sig_expr_set(struct aspeed_pinmux_data *ctx,
                                      const struct aspeed_sig_expr *expr,

diff --combined drivers/pinctrl/intel/pinctrl-baytrail.c
index 297b7b5fcb28df6776f919dfcde750deda59da5a,db6c5ca9e2d6ae734e1fe7314924df0463332899..9ffb22211d2b007ff70cc99d4caf5403ef0609c3
--- 1/drivers/pinctrl/intel/pinctrl-baytrail.c
--- 2/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@@ -98,13 -98,6 +98,6 @@@ struct byt_gpio_pin_context 
        u32 val;
  };
  
- struct byt_community {
-       unsigned int pin_base;
-       size_t npins;
-       const unsigned int *pad_map;
-       void __iomem *reg_base;
- };
- 
  #define COMMUNITY(p, n, map)          \
        {                               \
                .pin_base       = (p),  \
@@@ -112,26 -105,14 +105,14 @@@
                .pad_map        = (map),\
        }
  
- struct byt_pinctrl_soc_data {
-       const char *uid;
-       const struct pinctrl_pin_desc *pins;
-       size_t npins;
-       const struct intel_pingroup *groups;
-       size_t ngroups;
-       const struct intel_function *functions;
-       size_t nfunctions;
-       const struct byt_community *communities;
-       size_t ncommunities;
- };
- 
  struct byt_gpio {
        struct gpio_chip chip;
        struct platform_device *pdev;
        struct pinctrl_dev *pctl_dev;
        struct pinctrl_desc pctl_desc;
        raw_spinlock_t lock;
-       const struct byt_pinctrl_soc_data *soc_data;
-       struct byt_community *communities_copy;
+       const struct intel_pinctrl_soc_data *soc_data;
+       struct intel_community *communities_copy;
        struct byt_gpio_pin_context *saved_context;
  };
  
@@@ -383,11 -364,11 +364,11 @@@ static const struct intel_function byt_
        FUNCTION("gpio", byt_score_gpio_groups),
  };
  
- static const struct byt_community byt_score_communities[] = {
+ static const struct intel_community byt_score_communities[] = {
        COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
  };
  
- static const struct byt_pinctrl_soc_data byt_score_soc_data = {
+ static const struct intel_pinctrl_soc_data byt_score_soc_data = {
        .uid            = BYT_SCORE_ACPI_UID,
        .pins           = byt_score_pins,
        .npins          = ARRAY_SIZE(byt_score_pins),
@@@ -496,11 -477,11 +477,11 @@@ static const struct intel_function byt_
        FUNCTION("gpio", byt_sus_gpio_groups),
  };
  
- static const struct byt_community byt_sus_communities[] = {
+ static const struct intel_community byt_sus_communities[] = {
        COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
  };
  
- static const struct byt_pinctrl_soc_data byt_sus_soc_data = {
+ static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
        .uid            = BYT_SUS_ACPI_UID,
        .pins           = byt_sus_pins,
        .npins          = ARRAY_SIZE(byt_sus_pins),
@@@ -549,11 -530,11 +530,11 @@@ static const unsigned int byt_ncore_pin
        3, 6, 10, 13, 2, 5, 9, 7,
  };
  
- static const struct byt_community byt_ncore_communities[] = {
+ static const struct intel_community byt_ncore_communities[] = {
        COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
  };
  
- static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
+ static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
        .uid            = BYT_NCORE_ACPI_UID,
        .pins           = byt_ncore_pins,
        .npins          = ARRAY_SIZE(byt_ncore_pins),
@@@ -561,17 -542,17 +542,17 @@@
        .ncommunities   = ARRAY_SIZE(byt_ncore_communities),
  };
  
- static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
+ static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
        &byt_score_soc_data,
        &byt_sus_soc_data,
        &byt_ncore_soc_data,
        NULL
  };
  
- static struct byt_community *byt_get_community(struct byt_gpio *vg,
-                                              unsigned int pin)
+ static struct intel_community *byt_get_community(struct byt_gpio *vg,
+                                                unsigned int pin)
  {
-       struct byt_community *comm;
+       struct intel_community *comm;
        int i;
  
        for (i = 0; i < vg->soc_data->ncommunities; i++) {
@@@ -586,7 -567,7 +567,7 @@@
  static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
                                  int reg)
  {
-       struct byt_community *comm = byt_get_community(vg, offset);
+       struct intel_community *comm = byt_get_community(vg, offset);
        u32 reg_offset;
  
        if (!comm)
@@@ -605,7 -586,7 +586,7 @@@
                break;
        }
  
-       return comm->reg_base + reg_offset + reg;
+       return comm->pad_regs + reg_offset + reg;
  }
  
  static int byt_get_groups_count(struct pinctrl_dev *pctldev)
@@@ -1211,7 -1192,7 +1192,7 @@@ static void byt_gpio_dbg_show(struct se
        u32 conf0, val;
  
        for (i = 0; i < vg->soc_data->npins; i++) {
-               const struct byt_community *comm;
+               const struct intel_community *comm;
                const char *pull_str = NULL;
                const char *pull = NULL;
                void __iomem *reg;
@@@ -1455,20 -1436,6 +1436,20 @@@ static void byt_gpio_irq_handler(struc
        chip->irq_eoi(data);
  }
  
 +static void byt_init_irq_valid_mask(struct gpio_chip *chip,
 +                                  unsigned long *valid_mask,
 +                                  unsigned int ngpios)
 +{
 +      /*
 +       * FIXME: currently the valid_mask is filled in as part of
 +       * initializing the irq_chip below in byt_gpio_irq_init_hw().
 +       * when converting this driver to the new way of passing the
 +       * gpio_irq_chip along when adding the gpio_chip, move the
 +       * mask initialization into this callback instead. Right now
 +       * this callback is here to make sure the mask gets allocated.
 +       */
 +}
 +
  static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
  {
        struct gpio_chip *gc = &vg->chip;
@@@ -1539,7 -1506,7 +1520,7 @@@ static int byt_gpio_probe(struct byt_gp
        gc->can_sleep   = false;
        gc->parent      = &vg->pdev->dev;
        gc->ngpio       = vg->soc_data->npins;
 -      gc->irq.need_valid_mask = true;
 +      gc->irq.init_valid_mask = byt_init_irq_valid_mask;
  
  #ifdef CONFIG_PM_SLEEP
        vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
@@@ -1580,7 -1547,7 +1561,7 @@@
  }
  
  static int byt_set_soc_data(struct byt_gpio *vg,
-                           const struct byt_pinctrl_soc_data *soc_data)
+                           const struct intel_pinctrl_soc_data *soc_data)
  {
        int i;
  
@@@ -1593,15 -1560,13 +1574,13 @@@
                return -ENOMEM;
  
        for (i = 0; i < soc_data->ncommunities; i++) {
-               struct byt_community *comm = vg->communities_copy + i;
-               struct resource *mem_rc;
+               struct intel_community *comm = vg->communities_copy + i;
  
                *comm = vg->soc_data->communities[i];
  
-               mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0);
-               comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc);
-               if (IS_ERR(comm->reg_base))
-                       return PTR_ERR(comm->reg_base);
+               comm->pad_regs = devm_platform_ioremap_resource(vg->pdev, 0);
+               if (IS_ERR(comm->pad_regs))
+                       return PTR_ERR(comm->pad_regs);
        }
  
        return 0;
@@@ -1615,8 -1580,8 +1594,8 @@@ static const struct acpi_device_id byt_
  
  static int byt_pinctrl_probe(struct platform_device *pdev)
  {
-       const struct byt_pinctrl_soc_data *soc_data = NULL;
-       const struct byt_pinctrl_soc_data **soc_table;
+       const struct intel_pinctrl_soc_data *soc_data = NULL;
+       const struct intel_pinctrl_soc_data **soc_table;
        struct acpi_device *acpi_dev;
        struct byt_gpio *vg;
        int i, ret;
@@@ -1625,7 -1590,7 +1604,7 @@@
        if (!acpi_dev)
                return -ENODEV;
  
-       soc_table = (const struct byt_pinctrl_soc_data **)device_get_match_data(&pdev->dev);
+       soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(&pdev->dev);
  
        for (i = 0; soc_table[i]; i++) {
                if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {

diff --combined drivers/pinctrl/intel/pinctrl-cherryview.c
index ab681d1a3a7440b22c5ceccae8c2e6174f55f0f1,cfb7168fe76683e044ea9db88c5dcac331477261..aae51c507f590e77c854a3547779995ea227e7e4
--- 1/drivers/pinctrl/intel/pinctrl-cherryview.c
--- 2/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@@ -1543,30 -1543,6 +1543,30 @@@ static const struct dmi_system_id chv_n
        {}
  };
  
 +static void chv_init_irq_valid_mask(struct gpio_chip *chip,
 +                                  unsigned long *valid_mask,
 +                                  unsigned int ngpios)
 +{
 +      struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
 +      const struct chv_community *community = pctrl->community;
 +      int i;
 +
 +      /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
 +      for (i = 0; i < community->npins; i++) {
 +              const struct pinctrl_pin_desc *desc;
 +              u32 intsel;
 +
 +              desc = &community->pins[i];
 +
 +              intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
 +              intsel &= CHV_PADCTRL0_INTSEL_MASK;
 +              intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
 +
 +              if (intsel >= community->nirqs)
 +                      clear_bit(i, valid_mask);
 +      }
 +}
 +
  static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
  {
        const struct chv_gpio_pinrange *range;
@@@ -1581,8 -1557,7 +1581,8 @@@
        chip->label = dev_name(pctrl->dev);
        chip->parent = pctrl->dev;
        chip->base = -1;
 -      chip->irq.need_valid_mask = need_valid_mask;
 +      if (need_valid_mask)
 +              chip->irq.init_valid_mask = chv_init_irq_valid_mask;
  
        ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
        if (ret) {
@@@ -1601,6 -1576,21 +1601,6 @@@
                }
        }
  
 -      /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
 -      for (i = 0; i < community->npins; i++) {
 -              const struct pinctrl_pin_desc *desc;
 -              u32 intsel;
 -
 -              desc = &community->pins[i];
 -
 -              intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
 -              intsel &= CHV_PADCTRL0_INTSEL_MASK;
 -              intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
 -
 -              if (need_valid_mask && intsel >= community->nirqs)
 -                      clear_bit(i, chip->irq.valid_mask);
 -      }
 -
        /*
         * The same set of machines in chv_no_valid_mask[] have incorrectly
         * configured GPIOs that generate spurious interrupts so we use
@@@ -1677,7 -1667,6 +1677,6 @@@ static int chv_pinctrl_probe(struct pla
  {
        struct chv_pinctrl *pctrl;
        struct acpi_device *adev;
-       struct resource *res;
        acpi_status status;
        int ret, irq, i;
  
@@@ -1707,16 -1696,13 +1706,13 @@@
                return -ENOMEM;
  #endif
  
-       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
+       pctrl->regs = devm_platform_ioremap_resource(pdev, 0);
        if (IS_ERR(pctrl->regs))
                return PTR_ERR(pctrl->regs);
  
        irq = platform_get_irq(pdev, 0);
-       if (irq < 0) {
-               dev_err(&pdev->dev, "failed to get interrupt number\n");
+       if (irq < 0)
                return irq;
-       }
  
        pctrl->pctldesc = chv_pinctrl_desc;
        pctrl->pctldesc.name = dev_name(&pdev->dev);

diff --combined drivers/pinctrl/pinctrl-stmfx.c
index dd5aa9a2dfe545bb5c1315ac0bfbb3daf67fd6bf,d7e37b51984fe54b647bfefff4e33fcec31e223e..974973777395d13ef1409d2d721c84ec1fac99ba
--- 1/drivers/pinctrl/pinctrl-stmfx.c
--- 2/drivers/pinctrl/pinctrl-stmfx.c
+++ b/drivers/pinctrl/pinctrl-stmfx.c
@@@ -296,29 -296,29 +296,29 @@@ static int stmfx_pinconf_set(struct pin
                switch (param) {
                case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
                case PIN_CONFIG_BIAS_DISABLE:
+               case PIN_CONFIG_DRIVE_PUSH_PULL:
+                       ret = stmfx_pinconf_set_type(pctl, pin, 0);
+                       if (ret)
+                               return ret;
+                       break;
                case PIN_CONFIG_BIAS_PULL_DOWN:
+                       ret = stmfx_pinconf_set_type(pctl, pin, 1);
+                       if (ret)
+                               return ret;
                        ret = stmfx_pinconf_set_pupd(pctl, pin, 0);
                        if (ret)
                                return ret;
                        break;
                case PIN_CONFIG_BIAS_PULL_UP:
-                       ret = stmfx_pinconf_set_pupd(pctl, pin, 1);
+                       ret = stmfx_pinconf_set_type(pctl, pin, 1);
                        if (ret)
                                return ret;
-                       break;
-               case PIN_CONFIG_DRIVE_OPEN_DRAIN:
-                       if (!dir)
-                               ret = stmfx_pinconf_set_type(pctl, pin, 1);
-                       else
-                               ret = stmfx_pinconf_set_type(pctl, pin, 0);
+                       ret = stmfx_pinconf_set_pupd(pctl, pin, 1);
                        if (ret)
                                return ret;
                        break;
-               case PIN_CONFIG_DRIVE_PUSH_PULL:
-                       if (!dir)
-                               ret = stmfx_pinconf_set_type(pctl, pin, 0);
-                       else
-                               ret = stmfx_pinconf_set_type(pctl, pin, 1);
+               case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+                       ret = stmfx_pinconf_set_type(pctl, pin, 1);
                        if (ret)
                                return ret;
                        break;
@@@ -585,24 -585,12 +585,24 @@@ static int stmfx_pinctrl_gpio_function_
        return stmfx_function_enable(pctl->stmfx, func);
  }
  
 +static int stmfx_pinctrl_gpio_init_valid_mask(struct gpio_chip *gc,
 +                                            unsigned long *valid_mask,
 +                                            unsigned int ngpios)
 +{
 +      struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
 +      u32 n;
 +
 +      for_each_clear_bit(n, &pctl->gpio_valid_mask, ngpios)
 +              clear_bit(n, valid_mask);
 +
 +      return 0;
 +}
 +
  static int stmfx_pinctrl_probe(struct platform_device *pdev)
  {
        struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
        struct device_node *np = pdev->dev.of_node;
        struct stmfx_pinctrl *pctl;
 -      u32 n;
        int irq, ret;
  
        pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL);
@@@ -620,10 -608,8 +620,8 @@@
        }
  
        irq = platform_get_irq(pdev, 0);
-       if (irq <= 0) {
-               dev_err(pctl->dev, "failed to get irq\n");
+       if (irq <= 0)
                return -ENXIO;
-       }
  
        mutex_init(&pctl->lock);
  
@@@ -662,7 -648,7 +660,7 @@@
        pctl->gpio_chip.ngpio = pctl->pctl_desc.npins;
        pctl->gpio_chip.can_sleep = true;
        pctl->gpio_chip.of_node = np;
 -      pctl->gpio_chip.need_valid_mask = true;
 +      pctl->gpio_chip.init_valid_mask = stmfx_pinctrl_gpio_init_valid_mask;
  
        ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
        if (ret) {
@@@ -680,6 -666,8 +678,6 @@@
        pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type;
        pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock;
        pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock;
 -      for_each_clear_bit(n, &pctl->gpio_valid_mask, pctl->gpio_chip.ngpio)
 -              clear_bit(n, pctl->gpio_chip.valid_mask);
  
        ret = gpiochip_irqchip_add_nested(&pctl->gpio_chip, &pctl->irq_chip,
                                          0, handle_bad_irq, IRQ_TYPE_NONE);

diff --combined drivers/pinctrl/qcom/Kconfig
index fa2c878214010c9480775c270bbc9516e5b64ad7,af44dafc35e7f658cf608b6fef4f5100df481f98..32fc2458b8eb98ded5a9fe7343ef5ce7dca2b320
--- 1/drivers/pinctrl/qcom/Kconfig
--- 2/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@@ -138,7 -138,6 +138,7 @@@ config PINCTRL_QCOM_SPMI_PMI
         select PINMUX
         select PINCONF
         select GENERIC_PINCONF
 +       select GPIOLIB_IRQCHIP
         select IRQ_DOMAIN_HIERARCHY
         help
           This is the pinctrl, pinmux, pinconf and gpiolib driver for the
@@@ -159,6 -158,15 +159,15 @@@ config PINCTRL_QCOM_SSBI_PMI
           which are using SSBI for communication with SoC. Example PMIC's
           devices are pm8058 and pm8921.
  
+ config PINCTRL_SC7180
+       tristate "Qualcomm Technologies Inc SC7180 pin controller driver"
+       depends on GPIOLIB && OF
+       select PINCTRL_MSM
+       help
+         This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+         Qualcomm Technologies Inc TLMM block found on the Qualcomm
+         Technologies Inc SC7180 platform.
+ 
  config PINCTRL_SDM660
         tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
         depends on GPIOLIB && OF

diff --combined drivers/pinctrl/qcom/pinctrl-msm.c
index b8a1c43222f805ca12fbd94abc52672723421e63,edecd653daa9df202c40f93eeab9798f01a0311c..763da0be10d6f22ab7bc231aad3809242f7bce28
--- 1/drivers/pinctrl/qcom/pinctrl-msm.c
--- 2/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@@ -593,37 -593,35 +593,36 @@@ static void msm_gpio_dbg_show(struct se
  #define msm_gpio_dbg_show NULL
  #endif
  
 -static int msm_gpio_init_valid_mask(struct gpio_chip *chip)
 +static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
 +                                  unsigned long *valid_mask,
 +                                  unsigned int ngpios)
  {
 -      struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
 +      struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
        int ret;
        unsigned int len, i;
 -      unsigned int max_gpios = pctrl->soc->ngpios;
        const int *reserved = pctrl->soc->reserved_gpios;
        u16 *tmp;
  
        /* Driver provided reserved list overrides DT and ACPI */
        if (reserved) {
 -              bitmap_fill(chip->valid_mask, max_gpios);
 +              bitmap_fill(valid_mask, ngpios);
                for (i = 0; reserved[i] >= 0; i++) {
 -                      if (i >= max_gpios || reserved[i] >= max_gpios) {
 +                      if (i >= ngpios || reserved[i] >= ngpios) {
                                dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
                                return -EINVAL;
                        }
 -                      clear_bit(reserved[i], chip->valid_mask);
 +                      clear_bit(reserved[i], valid_mask);
                }
  
                return 0;
        }
  
        /* The number of GPIOs in the ACPI tables */
-       len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL,
-                                                  0);
+       len = ret = device_property_count_u16(pctrl->dev, "gpios");
        if (ret < 0)
                return 0;
  
 -      if (ret > max_gpios)
 +      if (ret > ngpios)
                return -EINVAL;
  
        tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
@@@ -636,9 -634,9 +635,9 @@@
                goto out;
        }
  
 -      bitmap_zero(chip->valid_mask, max_gpios);
 +      bitmap_zero(valid_mask, ngpios);
        for (i = 0; i < len; i++)
 -              set_bit(tmp[i], chip->valid_mask);
 +              set_bit(tmp[i], valid_mask);
  
  out:
        kfree(tmp);
@@@ -654,6 -652,7 +653,6 @@@ static const struct gpio_chip msm_gpio_
        .request          = gpiochip_generic_request,
        .free             = gpiochip_generic_free,
        .dbg_show         = msm_gpio_dbg_show,
 -      .init_valid_mask  = msm_gpio_init_valid_mask,
  };
  
  /* For dual-edge interrupts in software, since some hardware has no
@@@ -996,12 -995,13 +995,13 @@@ static bool msm_gpio_needs_valid_mask(s
        if (pctrl->soc->reserved_gpios)
                return true;
  
-       return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0;
+       return device_property_count_u16(pctrl->dev, "gpios") > 0;
  }
  
  static int msm_gpio_init(struct msm_pinctrl *pctrl)
  {
        struct gpio_chip *chip;
+       struct gpio_irq_chip *girq;
        int ret;
        unsigned ngpio = pctrl->soc->ngpios;
  
@@@ -1015,8 -1015,7 +1015,8 @@@
        chip->parent = pctrl->dev;
        chip->owner = THIS_MODULE;
        chip->of_node = pctrl->dev->of_node;
 -      chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl);
 +      if (msm_gpio_needs_valid_mask(pctrl))
 +              chip->init_valid_mask = msm_gpio_init_valid_mask;
  
        pctrl->irq_chip.name = "msmgpio";
        pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
@@@ -1028,6 -1027,18 +1028,18 @@@
        pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
        pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
  
+       girq = &chip->irq;
+       girq->chip = &pctrl->irq_chip;
+       girq->parent_handler = msm_gpio_irq_handler;
+       girq->num_parents = 1;
+       girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
+                                    GFP_KERNEL);
+       if (!girq->parents)
+               return -ENOMEM;
+       girq->default_type = IRQ_TYPE_NONE;
+       girq->handler = handle_bad_irq;
+       girq->parents[0] = pctrl->irq;
+ 
        ret = gpiochip_add_data(&pctrl->chip, pctrl);
        if (ret) {
                dev_err(pctrl->dev, "Failed register gpiochip\n");
@@@ -1054,20 -1065,6 +1066,6 @@@
                }
        }
  
-       ret = gpiochip_irqchip_add(chip,
-                                  &pctrl->irq_chip,
-                                  0,
-                                  handle_edge_irq,
-                                  IRQ_TYPE_NONE);
-       if (ret) {
-               dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
-               gpiochip_remove(&pctrl->chip);
-               return -ENOSYS;
-       }
- 
-       gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq,
-                                    msm_gpio_irq_handler);
- 
        return 0;
  }
  
@@@ -1161,10 -1158,8 +1159,8 @@@ int msm_pinctrl_probe(struct platform_d
        msm_pinctrl_setup_pm_reset(pctrl);
  
        pctrl->irq = platform_get_irq(pdev, 0);
-       if (pctrl->irq < 0) {
-               dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
+       if (pctrl->irq < 0)
                return pctrl->irq;
-       }
  
        pctrl->desc.owner = THIS_MODULE;
        pctrl->desc.pctlops = &msm_pinctrl_ops;

diff --combined drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
index 442db15e0729285427b3cebf148d9f4004f17c57,6a6b41444234d27afa4208f785ea4b252f960180..f1fece5b9c06ab690340f420aceaf46b2717809b
--- 1/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
--- 2/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
@@@ -170,6 -170,8 +170,6 @@@ struct pmic_gpio_state 
        struct regmap   *map;
        struct pinctrl_dev *ctrl;
        struct gpio_chip chip;
 -      struct fwnode_handle *fwnode;
 -      struct irq_domain *domain;
  };
  
  static const struct pinconf_generic_params pmic_gpio_bindings[] = {
@@@ -749,6 -751,23 +749,6 @@@ static int pmic_gpio_of_xlate(struct gp
        return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
  }
  
 -static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 -{
 -      struct pmic_gpio_state *state = gpiochip_get_data(chip);
 -      struct irq_fwspec fwspec;
 -
 -      fwspec.fwnode = state->fwnode;
 -      fwspec.param_count = 2;
 -      fwspec.param[0] = pin + PMIC_GPIO_PHYSICAL_OFFSET;
 -      /*
 -       * Set the type to a safe value temporarily. This will be overwritten
 -       * later with the proper value by irq_set_type.
 -       */
 -      fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
 -
 -      return irq_create_fwspec_mapping(&fwspec);
 -}
 -
  static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
  {
        struct pmic_gpio_state *state = gpiochip_get_data(chip);
@@@ -768,6 -787,7 +768,6 @@@ static const struct gpio_chip pmic_gpio
        .request                = gpiochip_generic_request,
        .free                   = gpiochip_generic_free,
        .of_xlate               = pmic_gpio_of_xlate,
 -      .to_irq                 = pmic_gpio_to_irq,
        .dbg_show               = pmic_gpio_dbg_show,
  };
  
@@@ -793,11 -813,13 +793,13 @@@ static int pmic_gpio_populate(struct pm
        switch (subtype) {
        case PMIC_GPIO_SUBTYPE_GPIO_4CH:
                pad->have_buffer = true;
+               /* Fall through */
        case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
                pad->num_sources = 4;
                break;
        case PMIC_GPIO_SUBTYPE_GPIO_8CH:
                pad->have_buffer = true;
+               /* Fall through */
        case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
                pad->num_sources = 8;
                break;
@@@ -944,24 -966,46 +946,24 @@@ static int pmic_gpio_domain_translate(s
        return 0;
  }
  
 -static int pmic_gpio_domain_alloc(struct irq_domain *domain, unsigned int virq,
 -                                unsigned int nr_irqs, void *data)
 +static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip,
 +                                                unsigned int offset)
  {
 -      struct pmic_gpio_state *state = container_of(domain->host_data,
 -                                                   struct pmic_gpio_state,
 -                                                   chip);
 -      struct irq_fwspec *fwspec = data;
 -      struct irq_fwspec parent_fwspec;
 -      irq_hw_number_t hwirq;
 -      unsigned int type;
 -      int ret, i;
 -
 -      ret = pmic_gpio_domain_translate(domain, fwspec, &hwirq, &type);
 -      if (ret)
 -              return ret;
 -
 -      for (i = 0; i < nr_irqs; i++)
 -              irq_domain_set_info(domain, virq + i, hwirq + i,
 -                                  &pmic_gpio_irq_chip, state,
 -                                  handle_level_irq, NULL, NULL);
 +      return offset + PMIC_GPIO_PHYSICAL_OFFSET;
 +}
  
 -      parent_fwspec.fwnode = domain->parent->fwnode;
 -      parent_fwspec.param_count = 4;
 -      parent_fwspec.param[0] = 0;
 -      parent_fwspec.param[1] = hwirq + 0xc0;
 -      parent_fwspec.param[2] = 0;
 -      parent_fwspec.param[3] = fwspec->param[1];
 +static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
 +                                         unsigned int child_hwirq,
 +                                         unsigned int child_type,
 +                                         unsigned int *parent_hwirq,
 +                                         unsigned int *parent_type)
 +{
 +      *parent_hwirq = child_hwirq + 0xc0;
 +      *parent_type = child_type;
  
 -      return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 -                                          &parent_fwspec);
 +      return 0;
  }
  
 -static const struct irq_domain_ops pmic_gpio_domain_ops = {
 -      .activate = gpiochip_irq_domain_activate,
 -      .alloc = pmic_gpio_domain_alloc,
 -      .deactivate = gpiochip_irq_domain_deactivate,
 -      .free = irq_domain_free_irqs_common,
 -      .translate = pmic_gpio_domain_translate,
 -};
 -
  static int pmic_gpio_probe(struct platform_device *pdev)
  {
        struct irq_domain *parent_domain;
@@@ -971,7 -1015,6 +973,7 @@@
        struct pinctrl_desc *pctrldesc;
        struct pmic_gpio_pad *pad, *pads;
        struct pmic_gpio_state *state;
 +      struct gpio_irq_chip *girq;
        int ret, npins, i;
        u32 reg;
  
@@@ -1051,21 -1094,19 +1053,21 @@@
        if (!parent_domain)
                return -ENXIO;
  
 -      state->fwnode = of_node_to_fwnode(state->dev->of_node);
 -      state->domain = irq_domain_create_hierarchy(parent_domain, 0,
 -                                                  state->chip.ngpio,
 -                                                  state->fwnode,
 -                                                  &pmic_gpio_domain_ops,
 -                                                  &state->chip);
 -      if (!state->domain)
 -              return -ENODEV;
 +      girq = &state->chip.irq;
 +      girq->chip = &pmic_gpio_irq_chip;
 +      girq->default_type = IRQ_TYPE_NONE;
 +      girq->handler = handle_level_irq;
 +      girq->fwnode = of_node_to_fwnode(state->dev->of_node);
 +      girq->parent_domain = parent_domain;
 +      girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq;
 +      girq->populate_parent_fwspec = gpiochip_populate_parent_fwspec_fourcell;
 +      girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq;
 +      girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate;
  
        ret = gpiochip_add_data(&state->chip, state);
        if (ret) {
                dev_err(state->dev, "can't add gpio chip\n");
 -              goto err_chip_add_data;
 +              return ret;
        }
  
        /*
@@@ -1091,6 -1132,8 +1093,6 @@@
  
  err_range:
        gpiochip_remove(&state->chip);
 -err_chip_add_data:
 -      irq_domain_remove(state->domain);
        return ret;
  }
  
@@@ -1099,6 -1142,7 +1101,6 @@@ static int pmic_gpio_remove(struct plat
        struct pmic_gpio_state *state = platform_get_drvdata(pdev);
  
        gpiochip_remove(&state->chip);
 -      irq_domain_remove(state->domain);
        return 0;
  }
  
@@@ -1113,6 -1157,12 +1115,12 @@@ static const struct of_device_id pmic_g
        { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
        /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
        { .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
+       /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
+       { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
+       /* pm8150b has 12 GPIOs with holes on 3, r and 7 */
+       { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
+       /* pm8150l has 12 GPIOs with holes on 7 */
+       { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
        { },
  };