arm64: errata: Add detection for TRBE invalid prohibited states

TRBE implementations affected by Arm erratum #2038923 might get TRBE into
an inconsistent view on whether trace is prohibited within the CPU. As a
result, the trace buffer or trace buffer state might be corrupted. This
happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E,
followed by just a single context synchronization event before execution
changes from a context, in which trace is prohibited to one where it isn't,
or vice versa. In these mentioned conditions, the view of whether trace is
prohibited is inconsistent between parts of the CPU, and the trace buffer
or the trace buffer state might be corrupted. This adds a new errata
ARM64_ERRATUM_2038923 in arm64 errata framework.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki Poulose <suzuki.poulose@arm.com>
Cc: coresight@lists.linaro.org
Cc: linux-doc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/1643120437-14352-4-git-send-email-anshuman.khandual@arm.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index c9b30e6c2b6cd25437e745a8ff734419764f821f..e0ef3e9a4b8b463b250d26752361da7b23f674de 100644 (file)
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -54,6 +54,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A510     | #2064142        | ARM64_ERRATUM_2064142       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | Cortex-A510     | #2038923        | ARM64_ERRATUM_2038923       |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319        |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319        |

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 0033436e3416319882c39218c2f76a4535c8445e..fecf2b09e870a383b5403ddb5668858cdccbcc2a 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -796,6 +796,29 @@ config ARM64_ERRATUM_2064142
 
          If unsure, say Y.
 
+config ARM64_ERRATUM_2038923
+       bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
+       depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
+       default y
+       help
+         This option adds the workaround for ARM Cortex-A510 erratum 2038923.
+
+         Affected Cortex-A510 core might cause an inconsistent view on whether trace is
+         prohibited within the CPU. As a result, the trace buffer or trace buffer state
+         might be corrupted. This happens after TRBE buffer has been enabled by setting
+         TRBLIMITR_EL1.E, followed by just a single context synchronization event before
+         execution changes from a context, in which trace is prohibited to one where it
+         isn't, or vice versa. In these mentioned conditions, the view of whether trace
+         is prohibited is inconsistent between parts of the CPU, and the trace buffer or
+         the trace buffer state might be corrupted.
+
+         Work around this in the driver by preventing an inconsistent view of whether the
+         trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
+         change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
+         two ISB instructions if no ERET is to take place.
+
+         If unsure, say Y.
+
 config CAVIUM_ERRATUM_22375
        bool "Cavium erratum 22375, 24313"
        default y

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index cbb7d5a9aee79daf990923a7bd785f0cb6dd5a1e..60b0c1f1d91282dce77a24065dcfaf2a34b1dd7a 100644 (file)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -607,6 +607,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
                ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
        },
 #endif
+#ifdef CONFIG_ARM64_ERRATUM_2038923
+       {
+               .desc = "ARM erratum 2038923",
+               .capability = ARM64_WORKAROUND_2038923,
+
+               /* Cortex-A510 r0p0 - r0p2 */
+               ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
+       },
+#endif
        {
        }
 };

diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index fca3cb329e1dbcc18be4b8f82e2be441a8c1245b..45a06d36d080707ffbed8966e8e266b9cc26a448 100644 (file)
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -56,6 +56,7 @@ WORKAROUND_1463225
 WORKAROUND_1508412
 WORKAROUND_1542419
 WORKAROUND_2064142
+WORKAROUND_2038923
 WORKAROUND_TRBE_OVERWRITE_FILL_MODE
 WORKAROUND_TSB_FLUSH_FAILURE
 WORKAROUND_TRBE_WRITE_OUT_OF_RANGE